Abstracts of Available Literature

How to select a Compaction Technology
Extensive research and tests have shown that the highest quality results in the shortest time come from a compaction method using an edge-based scan line algorithm, which is employed by best-in-class compaction tools.
Today, layout compaction or conversion technology must solve many problems besides providing a small, DRC-correct layout. Designers have to consider circuit performance, power consumption, compatibility with existing design flows, and design verification when choosing a layout conversion tool.

This White Paper gives an overview of the technology and applications of the latest layout compaction methodology available on the market, and provides detailed information for making an educated evaluation of different tools in the market today. >>back

How to setup a Layout Migration Project 
The most preferred method for full custom design is the reuse of the physical layout. Therefore a growing number of designers is faced with the task of reusing a given design in a new technology without redesigning it from scratch. Beside the linear shrink method, there is not much experience in the industry of how to setup and manage the general task of converting a design to a deep submicron technology. 
The linear shrink method can consider only the geometrical changes of design rules. With a general conversion approach designers can consider electrical performance differences of the technologies and can also adjust the design to new performance needs like low power, high speed or different voltage levels.
This White Paper explains the different options of a conversion and provides a method to ensure that the performance goals of a conversion can be met. It also discusses different migration goals and the verification of the converted results.  >>back

How to solve Timing and Signal Integrity Problems 
During the last 20 years, converting an IC design to a more advanced CMOS technology always resulted in faster circuits. But today, shifting a design to ultra deep sub-micron (UDSM) technology with an 0.18-micron gate length does not guarantee a faster design. This is because, in UDSM technologies, a significant change has occurred in the relationship between the electrical parameters of wiring and transistors.

• This problem is, in general, called the timing problem, which is actually a mix of several problems occurring at the same time. These problems are: Limitations of the typical synthesis-based design flow accompanying huge design sizes.
• Increase of capacitance in the wiring caused by the aspect ratio of the wires.
• Reduced supply voltage levels and circuit speeds caused by smaller gate length.
• Higher circuit speeds, lower voltage levels, and greater capacitance cause crosstalk and transmission line effects which can, in turn, cause circuit failures.

All these effects are created in the last phase of the design, the physical layout, and are hard to anticipate in earlier design stages. Therefore, some companies work on a feedback loop, or on methods for analyzing potential problems on the VHDL or netlist level and controlling the physical design phase with these constraints. But these methods may not guarantee a solution. A different approach is to correct the physical design to eliminate these problems altogether. This White Paper describes a method to achieve this goal using compaction technology.  >>back