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Infrastructure for Design Reuse
Solve Timing and Signal Integrity Problems
An Effective Way of Design Reuse

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Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
Philips migrates microprocessor core
Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

QuaSA extracts electrical parameters from a layout, providing information for automatic layout manipulation, correction and compaction technology to ensure timing-correct layout manipulation.

Los Angeles, CA, June 5, 2000.....RUBICAD Corporation, a world-leading EDA supplier of layout, migration and optimization tools for physical circuit designs, today announced the introduction of QuaSA, a new integrated parasitic extraction and analysis tool that enables automatic correction of timing, signal integrity and power problems inside the physical layout database.

QuaSA stands for Qualified Signal Analysis. QuaSA extracts electrical parameters such as RC and power density from the physical layout. This data makes it possible to automatically create instructions and constraints for the LACE Layout Compaction Engine, which will modify the physical layout, so that it will meet the target specification. QuaSA can use different sources for the target specification, including the output of timing analyzers, annotated netlists, and the physical layout itself. QuaSA can be used to correct and optimize new designs, as well as for enabling design re-use during automatic layout migration. 

"QuaSA is the link between technology, electrical requirements, and the physical representation of a layout," said Michael Reinhardt, RUBICAD's president. "For IP reuse in the latest ultra deep sub-micron technologies, an intelligent technology mapping approach is necessary to reach performance goals. QuaSA is the only tool on the market that provides information about layout modification for timing closure, which can automatically be put into a layout modification tool such as RUBICAD's LACE. "

QuaSA can be used for several tasks:

1. Timing closure and timing optimization
QuaSA analyzes the layout and compares the physical implementation with the target delay specification from the timing analyzing tool. In case of discrepancies, QuaSA will use its detailed information for calculating constraints to modify the physical layout. The calculated constraints can be a signal-specific spacing requirement, a larger signal width, or a driver size modification. The resulting layout will satisfy the specification of the timing analyzer.

2. Removing the source of a signal integrity problem 
QuaSA combines signal integrity analysis together with timing analysis. This approach makes it possible to detect and analyze dynamic timing effects caused by crosstalk. From these analysis results, the constraints for the correction of the physical layout will be calculated.

3. QuaSA ensures timing-correct layout migration
Layout migration to ultra deep sub-micron (UDSM) technologies has to be timing-driven. This means that a migration tool must be able to control, check and modify the circuit timing. This process has to consider the source and target technology, as well as the specification for the target design. QuaSA makes it possible to compare circuits on the layout level and check whether the timing requirements are met. If the design needs modifications it will calculate the needed constraints, and the discrepancies can be corrected by a compaction tool.
 

The major benefits of using QuaSA are:

• QuaSA uses an innovative, time-saving approach for RC extraction, using high-speed scanline technology combined with electrical extraction technology. Therefore, large databases can be analyzed in the fastest possible time frame.
• QuaSA is integrated into LADEE and works seamlessly with CrossSpeed and LACE. This seamless integration produces an automatic flow of parasitic extraction, correction and verification possible.
• QuaSA works for all design styles, semi-custom as well as structured full custom. QuaSA can be applied to a standard cell design as well as to full custom structured layouts such as memory and datapath designs. 
• QuaSA works on a hierarchical database. This allows applying the method to hierarchical structured designs such as memories and datapath multipliers.

Why use QuaSA for Design Reuse in UDSM Designs?

The major difference between QuaSA and other extraction technology is that QuaSA extracts electrical information in combination with detailed topology information. This approach makes it possible to calculate commands and constraints to achieve the desired timing behavior of the circuit in the new technology.

In UDSM designs, interconnect delays dominate system performance. In this environment decreasing line widths lead to increased interconnect resistance, and decreasing interline separations lead to increased interconnect capacitance. 3D effects, such as interline fringing, become more dominant as conductors in deep sub-micron become taller relative to their width.
Therefore, it is difficult to achieve correct timing with traditional hard IP migration methods, such as a linear shrink and design rule correction. 
With QuaSA it is possible to match the timing of designs when converting them to a different technology. The characteristic and timing of each signal is extracted before conversion. After conversion the new design will be analyzed considering the new process parameters and compared with the characteristics of the design before conversion. In the case of discrepancies, the conversion flow will be automatically adjusted to correct the result. With this process, non-linear parameter changes can also be handled and design improvements such as speed increases and power reduction can be embedded into the conversion flow.

Pricing and Availability

QuaSA is a standalone tool that can be integrated into any design flow. A version that is integrated into the LADEE migration tool suite is also available. Special discounts are available for current LADEE customers. QuaSA runs on SUN, HP and Pentium workstations under SUN OS, Solaris, LINUX, and HPUX. Shipments begin in fourth quarter 2000.
 

About RUBICAD

RUBICAD Corporation is the pioneer in developing automatic layout migration and design software. The company addresses the physical design tool market, and offers layout migration and design tools and services.
Customers include major international IC manufacturers, semiconductor and fabless companies, and system manufacturers.

For more information, contact RUBICAD Corp., 111 North Market Street, Suite 940, San Jose, CA 95113, Tel. 408-995-3334, Fax: 408-995-3335, www.rubicad.net, info@rubicad.com

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LACE, LACEedit, LADEE, HierO, P-REX, CrossSpeed, and QuaSA are trademarks or registered trademarks of RUBICAD Corporation. All other trademarks are the respective property of their owners