Articles
Infrastructure for Design Reuse
Solve Timing and Signal Integrity Problems
An Effective Way of Design Reuse

Success Stories
Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
Philips migrates microprocessor core
Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

LACE 4.0 offers faster, parallel conversions of hard IP using multiple workstations, maintains design hierarchy, improves technology file setup time, and includes a layout editor

LACE converts hard intellectual property (IP) for use in deep submicron (DSM) System-on-a-chip (SoC) applications. With LACE, designers are able to maintain the predictability of reusing their proven hard IP while automatically optimizing it for specific fabs or technologies.

According to Michael Reinhardt, Rubicad's president: "Conceptually design reuse is the accepted strategy for developing SoC in a timely manner. LACE closes the gap between the concept and practice, because it enables designers to reuse approved hard IP and hard macros in DSM technologies while automatically adjusting and optimizing the design for the technical and electrical requirements of the latest technology."
Reinhardt added, "Several years of research resulted in our breakthrough technology for hierarchical compaction. LACE 4.0 is the only tool that hierarchically converts hard IP independent of the original design environment and the original process technology."

Hierarchical Design Conversion Turns Reuse of Hard IP into Reality:
LACE 4.0 uses an intelligent inter-process control algorithm to distribute a design over a local area network (LAN), and run a multi-level hierarchy design conversion in parallel. Using a parallel conversion methodology, LACE converts hard macros and hard cores as well as hard IP like RAM, ROM, DRAM, datapaths, and microprocessors while preserving a design's hierarchy.
Maintaining hierarchy in a layout database for memory or datapaths is a required precondition for using the converted design with verification and simulation tools. The converted design, which is still hierarchical, can again be simulated and verified on a higher design level to shorten simulation and verification time. The new version of LACE offers increased user friendliness. The expertise, which was collected during hundreds of different conversion tasks, is now part of pre-defined conversion and optimization templates that a novice user can select. These new templates cover the majority of conversion tasks for compaction, optimization, design rule correction, and increased performance. They also reduce the initial setup time up to 80% for an average technology  conversion.

About DSM Design Reuse of Hard IP:
Re-using approved pre-DSM era IP is now almost impossible. In the pre-DSM era, linear shrink was a technique used to successfully convert physical designs. Now, for technologies of 0.35 micron and below design rules don't shrink linearly with the same scaling factor. Some rules become much smaller than others do, some remain the same, and some become sometimes bigger. Devices and transistors have to be re-sized according to the new technology's  performance. To re-place and route, re-synthesize a design or even do a re-layout manually ends in a time-consuming solution which is unable to stand the market pressure of short product life cycles. DSM technologies require a more flexible approach, because for performance, yield, area and electromigration requirements the design needs to be adjusted to the optimum technical feature sizes.
LACE enables designers to dramatically reduce development cycles and shorten time-to-market for SOC designs independent of their design environment and design style. With LACE designers convert physical designs for reuse in their SoCs and with newer DSM technologies. LACE combines the predictability of hard IP while automatically optimize hard IP for a specific fab or technology.

LACE includes LACEedit, a layout polygon editor, for creating and editing layout for quick design rule corrections and conversions.

Pricing and availability:
LACE 4.0 is available in September for UNIX and Linux users on SUN, HP and Pentium. Several licensing options are available.

About Rubicad:
Rubicad Corporation is the pioneer in developing automatic layout migration software. The company addresses the physical design tool market, and offers layout and migration tools and services. Customers include major international IC manufacturers, semiconductor and fabless companies, and systems manufacturers.

For information contact Rubicad Corp., 111 North Market Street Suite 940, San Jose, CA 95113, 408-995-3334, FAX: 408-995-3335, info@rubicad.com

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LACE is a registered trademark and LACEedit is a trademark of Rubicad Corp.
All other trademarks are the properties of their respective owners.

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