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Archive
1996
1997
1998
1999
2000
2001
Articles
Infrastructure
for Design Reuse
Solve Timing and
Signal Integrity Problems
An Effective Way
of Design Reuse
Success Stories
Synopsys
chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine
cuts design time and costs
IMI increases
performance
OKI
reuses
Hard IP
Philips migrates
microprocessor core
Qualcomm
optimizes Standard Cell Libraries
Xilinx
migrates
FPGA |
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October
99
HierO Evaluates Layout for Area Optimization
of Hierarchical IC Layout
HierO [he:ro:] shows the effect on overall
area of a design for optimized and non-optimized hierarchical cells. >>more
June 99
CrossSpeed Provides Unique, But Obvious,
Method for Solving Deep Sub-Micron Problems
CrossSpeed solves timing, signal integrity
and power problems in deep-submicron (DSM) technology by reducing wire
resistance and wire capacitance on the physical layout level. >>more
January 99
LADEE, the New Physical Design Environment
Solves Signal Integrity, Power and Timing Problems in Deep-Submicron.
LADEE solves signal integrity problems
like crosstalk, as well as timing and power problems on the physical design
level by combining layout verification with layout compaction technology.
>>more
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