Events
CICC 2002
DAC 2002

Articles
Infrastructure for Design Reuse
Solve Timing and Signal Integrity Problems
An Effective Way of Design Reuse

Success Stories
Alpha CPU goes 0.13 micron
Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
Philips migrates microprocessor core
Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

Presentation outlining the solution for solving the most pressing design problems will be repeated at Design Automation Conference New Orleans in June.

San Jose, CA, May 15, 2002..... RUBICAD Corporation, a world-leading EDA supplier of layout manipulation and optimization tools for physical circuit designs, was awarded first prize for the most informative presentation at the Custom Integrated Circuit Conference in Orlando from May 13-14, 2002. Michael Reinhardt, President and CEO of RUBICAD discussed how to solve the most pressing design problems through Automatic Layout Modification (ALM) on the physical design level. 
The presentation covered solutions for timing and signal interity problems, power and yield issues, as well as the automatic correction of ultra deep sub-micron rules that were non-existent in previous technologies.
Due to the huge success of the presentation, RUBICAD will repeat the presentation at this year’s Design Automation Conference from June 10-14, 2002 in New Orleans. Participants can sign up at RUBICAD’s website www.rubicad.net or by calling 877-RUBICAD to reserve a seat for the presentation.
At Design Automation Conference, Michael Reinhardt’s book Automatic Layout Modification will also be offered for the first time by Kluwer Academic Publishers, Norwell, MA. 

Solving design problems on the physical level
Ultra deep submicron technologies have become main stream over the last few years. These technologies allow the integration of over 100 million transistors at the 0.13 micron level and it is expected that over 500 million transistors can be integrated on a single chip by 2008. However, designing in these new technologies require a more sophisticated physical design approach.

For several years, ASIC engineers have been plagued by timing problems in ultra deep sub-micron technologies. Timing closure is more difficult to achieve in deep sub-micron processes. The reasons are well known - the relation between wire delay and gate delay is increasing. Wire delays are becoming much larger than gate delays. RUBICAD’s ALM technology provides an automatic solution for adjusting designs post-layout and solving the majority of timing problems.

Another main concern for ASIC designers is signal integrity. In 0.13 technologies most designs are affected by crosstalk. This is because of lower supply voltage levels, faster circuit speeds and larger wire capacitances. Noise levels, which were uncritical before, have suddenly become critical and now have an adverse effect on circuit timing and functionality. RUBICAD’s ALM technology helps to modify the physical design so that signal integrity problems can be avoided. 

Yet another challenge for designers is power. Power consumption is thought to be controlled best at the architectural level. However, improvements in power reduction can be successfully achieved by modifying the physical design using RUBICAD’s ALM technology.

RUBICAD’s ALM technology can also be applied towards yield improvement. Recent semiconductor data revealed that yields are only 50% - 60% in 0.13 micron technologies. This is significantly lower than the 90% plus designers were used to in 0.18 and 0.25 micron technologies.
Here again RUBICAD’s ALM technology is the ideal solution to solve yield problems without increasing die size by adjusting the physical layout.

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