Articles
Infrastructure for Design Reuse
Solve Timing and Signal Integrity Problems
An Effective Way of Design Reuse

Success Stories
Alpha CPU goes 0.13 micron
Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
Philips migrates microprocessor core
Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

OKI Automatically Migrates Hard IP from Different Sources For Reuse in Embedded Applications Using Rubicad's LACE

How OKI benefits from Deep-Submicron Technologies by building New Silicon Systems in a Short Timeframe

Takahiro Takechi, OKI Tokyo, Japan

The Challenge - Choosing the Best Design Reuse Method
In today's competitive, fast-changing semiconductor market, IC design centers and manufacturers must respond quickly to new, more advanced technologies. Today, it is essential to reuse existing designs to build new silicon systems in the latest deep-submicron technology. Deep-submicron technologies enable the creation of circuits with tens of millions of transistors. The industry knows that designing these circuits from scratch every time is not the way to stay competitive. But the question is-what is the best method for design reuse? Is it more efficient to use VHDL description and re-synthesize the circuit, to migrate an existing hard macro, or do a combination of both? Key issues must be evaluated and tradeoffs must be made. One thing is certain-the short product life cycle and short introduction time of new silicon fabrication technologies demand a change in traditional circuit design.

Design Reuse in Various Flavors

Most Common Choice-Re-Synthesize
When considering design reuse, most engineers opt to reuse a VHDL model and re-synthesize a design. This approach has worked well previously with noncritical designs. The ideal solution was that all the designer needed to do was to push a button to have a layout design through place and route with a new library in a new technology. However, since deep-submicron technology, this approach is no longer pushbutton in every case. After a critical design is placed and routed, a post-layout simulation is required because the assumption of zero interconnect delay is obsolete. Designers need to extract capacitance and resistance and verify the timing behavior of the layout. If the simulation results are unsatisfactory, engineers must either modify the netlist or the way the place and route tool is working. Often final layout modifications are done manually. These manual modifications cause problems when the design is reused in another technology because the documentation of the original design is insufficient. Specifics of why and where final fixes in a layout are not documented because reuse was not a consideration when the layout was originally created. To recreate the layout from the existing VHDL description, the same process and the same time must be duplicated. Engineers must know the original design to make it work properly a second time.

One Company’s Choice-Successful use of Rubicad’s LACE
OKI optimized their hard macros using LACE, Rubicad’s Layout Conversion Environment. As a result, OKI is able to build new silicon systems reusing hard IP from different sources and combining them in new embedded applications.

With Rubicad’s LACE, OKI saves time and reduces costs in three important areas:

• Designs are available in the latest deep-submicron technology in a fraction of the time it used to take; thus, new products are to market several months earlier.
• Converted libraries are available several months earlier; therefore, new designs can be created several months earlier than with the old manual library conversion. This decreases the time to market and increases the market window for new products.
• OKI integrates already working and silicon-proven, third-party designs into their applications, thereby creating various new products.

Requirements for the Migration of IC Layout for Reuse in Embedded Silicon Systems
To ensure that the layout of an existing design like a microprocessor or DSP cores fits in a new silicon system, two conditions must be met:

Timing of the converted core or macro must fit into the context of the complete new system. The migration process needs to adjust signal and power lines as well as transistor sizes.

Geometrical design rules, grid values, substrate density, etc. must meet exactly the requirements of the new process technology so that when the core or macro is integrated into the new system, no optical manipulation can make the core work in the new system.

Challenge of Reusing Existing Layout Designs for New Silicon Systems
Though the layouts are polygon data, in many cases documentation of the original design is unavailable or insufficient because the original design was not considered for reuse in a different context.

If the original designer made some tricky fixes like widening a specific signal to meet timing or shifting signals further apart to avoid crosstalk, they are not documented in the layout. During conversion to a new technology, these special fixes must be considered. Without documentation, this is difficult and a careful verification is required after conversion. Timing verification is important within conversion to deep-submicron technology. Therefore, in the future the conversion software must interface with a timing check tool so that if the results of timing verification do not meet requirements, the conversion tool automatically fixes them through reconversion with different parameters.

Best Results through Careful Upfront Preparation
To successfully reuse existing designs in new silicon systems in deep-submicron technology, careful preparation reduces project time. The most efficient way is to compare the original technology and the target technology by simulating the performance of both and then comparing the speed, geometrical dimensions, and feature sizes of both technologies. Thus, an accurate prediction can be made about the performance of the converted layout.

Having the right methodology and tool suite in place maximizes the success of design reuse. OKI found the solution in Rubicad’s LACE because this method satisfies our requirements for area reduction, cost savings, and, most importantly, time savings.

OKI Successfully uses LACE for Conversion
Recently we had to build a new ASIC chip for a communication system. The chip consists of a processor core, RAM, analog blocks, etc. The requirement was that we implement an existing full custom microprocessor core which had about 80,000 transistors and was originally designed for another application in an older 0.5-micron technology. The new chip had to be produced in our newer 0.35- and 0.25-micron technology. Because the microprocessor core was designed for another fab, we could not simply shrink it to the 0.35- and 0.25-micron technology. When we build embedded chips, all parts which we reuse or design new must be optimized for the technology for which we produce the chip.

The solution to map the third-party, full custom microprocessor core for our technology is to automatically convert it with LACE. The common flow for our conversion is as follows:

We compare the original technology and the target technology by simulating design portions in both technologies so we can make some estimates about the core performance.
If the simulation results are sufficient, we establish a specification for the core which should be converted.

Based on the results of the simulation and our specification requirements, we decide on the shrink ratio of the transistor size. The shrink ratio for the transistors is sometimes different than the overall shrink factor because of the performance difference between the original technology and target technology.

We set up LACE for the specific layout style and the target technology and automatically convert the layout of the microprocessor core.

After conversion to the new technology, we check for DRC errors with our standard design rule check tool to ensure that the converted design will pass our signoff procedures.
Then we extract capacitance and resistance of the converted layout and verify the timing of the layout in the new process technology using verification tools like TimeMill from Epic/Synopsys.

If the performance of the converted layout does not meet our specification, we put a different factor for the transistor sizing in the critical area of the design and let LACE run another conversion with different transistor sizing. If the modification needed to meet the performance requirements is minor, we correct the layout manually.

If we have a critical design, we simulate critical parts of the converted design on the transistor level using Hspice.

The automatic layout conversion of the microprocessor design for this embedded application was done in two months.

Within the two-month timeframe for each process, LACE was set up for the layout style and guidelines of the microprocessor. To ensure correct technology file setup, we run external design rule and LVS checks with our standard check tool. Once LACE is set up; the conversion run for the 80,000 transistor core needs only two to four days depending on which machine we use to run the conversion.

After the first run if we discover that we need to change the sizing factor for the transistors or wires, it is no problem with LACE. One or two numbers must be changed in the technology setup, and after a second conversion run, the layout matches the requirements.

Before LACE when we converted our own designs or third-party designs to the next process technology, we did a linear shrink and manual design rule fixing. At that time we invested much effort to make external designs work in our process.

LACE outperformed the manual method for two important reasons:

LACE compacted the layout to the densest possible structure in a given technology. Using a linear shrink approach usually requires a compromise and sacrifices some area. Of course our layout designer can make the shrunk and manually corrected layout smaller, too. However, the drawback is that the manual work takes four to five times longer than the automatic conversion method.

The automatic layout conversion of a library using LACE required only 15 to 20% of the time used for manual fixing. And the shrink with manual fixing did not result in smaller area or time savings.

OKI’s Other Specialties
At OKI we not only convert hard IP like microprocessors or DSP cores across process technologies and across fabs, we also convert our standard cell libraries. If we create a special process for one of our customers, we have a brief period for product design. We do not have time to create a new library manually because we must get our new products to market as soon as possible. And LACE helps us do this by creating a new library within a few weeks instead of months.

LACE's Other Benefits and Design Possibilities
LACE’s fast conversion time offers several new design possibilities for us:

Library Conversion: It can be used to create libraries targeted toward specific applications by defining design parameters, such as transistor width and power bus width, according to the needs of the particular design. Libraries can be created for small, medium, and large circuits; high- or low-speed; and high- or low-voltage applications. Designers also can create personal libraries containing only the cells they need for a particular design so that those cells can be recompacted for optimum size.

Block Conversion: LACE can be used to convert whole blocks of pre-routed standard cells or full custom macro blocks. In performing the layout conversion, LACE maintains the hierarchy and the same relative positions of the devices inside the layout and the same relative capacitance and resistance. It reduces power consumption in pre-routed standard cell blocks by adjusting transistor sizes as needed.

Third-Party Layout Conversion: With LACE, layouts can be converted to a new fabrication technology without human knowledge or understanding of the layouts’ circuit details. This capability is important to us because we use third-party circuits that were not designed by our team. Before we had LACE, we had to convert layout designs manually, a time-consuming task.

The bottom line is that LACE is a big win for our layout and design teams.

Back to Top