| Published March
2000 Rubicad News
Peregrine Semiconductor
cuts die size and costs through layout compaction
An Interview with Jim Cable, VP of Technology
& Engineering by Gabriele Eckert
Peregrine is one of the leaders in Silicon
On Insulator (SOI) CMOS technology for various types of wireless and high-speed
mixed-signal products. Dr. Jim Cable is Vice President of Technology &
Engineering at Peregrine. He has more than 19 years of experience
in semiconductor research, development and production.
???
Recently
RUBICAD did a layout migration project for Peregrine Semiconductor. Can
you tell our readers a little about this project?
The product is a phase lock loop for cell
phone/pager applications. It's a true type of RF product and runs
at 1.8 GHz. It has a high percentage of analog circuit. Because of the
requirements of the synthesizer in terms of phase noise and low power,
the actual implementation of the analog part is very important, and is
done using a full custom design methodology. The digital part of
the PLL implements the low frequency divider and is running at about
100 MHz.
The design has about 5000 digital transistors
and we were interested to shrink the area of the chip, because of the pricing
pressures we have on that product.
RUBICAD compacted the digital part of
the layout for us by using their layout and migration tool suite LADEE.
We manually modified the analog part of that particular design and we currently
have received our first silicon of that product.
???
Can
you tell us more about Peregrine and its technology?
The product is a phase lock loop for cell
phone/pager applications. It's a true type of RF product and runs
at 1.8 GHz. It has a high percentage of analog circuits. Because of the
requirements of the synthesizer in terms of phase noise and low power,
the actual implementation of the analog part is very important, and is
done using a full custom design methodology. The digital part of
the PLL implements the low frequency divider and is running at about 100
MHz.
The design has about 5,000 digital transistors
and we were interested in shrinking the area of the chip, because of the
pricing pressures we have on that product. RUBICAD compacted the digital
part of the layout for us by using their layout and migration tool suite
LADEE. We manually modified the analog part of that particular design and
we currently have received our first silicon of that product.
???
What
are the most important reasons to use a layout compaction method versus
other methods to shift the design to another technology?
The reason we chose the automatic layout
compaction method was simply the fast turn around time and our time-to-market
pressure. Our alternative would have been to draw the circuit manually
anew. We asked RUBICAD to do the compaction job in 10 working days and
they finished it within six days, which we were quite pleased with. It
was a very tight schedule. The performance requirements of the design were
not very demanding. We needed to shrink the die to get the costs down.
Automatic compaction using the layout
migration software made the most sense to reach our goal quickly.
???
What
was the largest benefit for you of getting the layout migration done by
RUBICAD's design service?
RUBICAD are the experts in layout compaction
and migration. They had complete knowledge of the migration technology,
so they could do it quickly. There would have been a learning curve for
us to get up to speed with the migration software. Learning new tools is
not always trivial. I have a high confidence level in their service.
???
Did
the layout area and layout quality meet your, and your design team's, expectation?
We expected an area reduction of 30% and
RUBICAD achieved 30%. We were very pleased with the performance.We could
modify the analog part of the design and reduced the area by 20% so that
our overall reduction was 20%.
???
Was
there additional manual work necessary, caused by the layout compactor,
to make the layout pass DRC and LVS?
No. The layout we received from RUBICAD
was 100% DRC and LVS clean. Another requirement was, that the compacted
layout keeps exactly the irregular shape it had before.
RUBICAD did an excellent job on that.
You can see that on the plots on this page. It was important to us to keep
the same shape, because we needed to arrange the analog and RF circuitry
around the compacted parts just as they were before migration. The reason
is that we wanted to maintain the same analog performance we had before.
Without any problem, we took the compacted layout and put it together with
the analog parts, which we modified manually
???
Can
you tell us what your design team thought about the migration project?
We were quite pleased. RUBICAD did exactly
what they said they would do for us.
???
What
are the recommendations you can suggest to other design teams who need
to migrate their designs to different technologies or reuse them in silicon
systems?
We are primarily a very high-speed technology
company. Most of the designs we do are handcrafted down to the transistor
level. The digital part is usually smaller than the analog part. To migrate
to other technologies by using RUBICAD's migration technology should work
very well for us. Certainly, the RUBICAD migration technology makes sense
for what we wanted to do. Going forward we can see several more migration
projects to continue to reduce die size. We are in a very, very cost competitive
market, so die size is a critical issue.
???
What
applications do you see for a layout compaction technology?
More and more, customers are asking us
to put more digital logic on a chip to create more of a wireless system-on-a-chip.
We are also creating products thatneed to integrate external Intellectual
Property. We see more and more customer requests to add more digital portions
to our products in the area of 50 - 70 K transistors, such as micro-controllers.
The fastest way would probably be to use so-called hard IP, which is the
physical layout. In this case, layout migration technology will be required
to convert designs in other CMOS processes to our special UTSi process.
Another potential application is that we need to migrate to other fab design
rules, because in the future we will have more foundry partners. We are
projecting products in 0.35- and 0.25-micron technology.
Thirdly, we are looking for the capability
of die size reduction. Layout compaction will definitely help us to reduce
die size and get out more chips per wafer.
???
How
did you learn about RUBICAD's service and products?
I honestly don't know. Our engineers evaluated
several companies in the field of layout migration and RUBICAD's results
looked better than those from the competitors.
???
Have
you done automatic layout compaction before you did this project with RUBICAD?
What was your experience?
Nobody here at Peregrine had any experience
with automatic layout migration before. We were very pleased with the service
we got. RUBICAD was very customer responsive and receptive doing the work.
At some point in time, we might bring in RUBICAD's migration technology
and do the layout migration and optimization ourselves.
???
Which
factors most influenced your decision to work with RUBICAD for your layout
migration product?
RUBICAD was much more receptive than the
competitors. We needed to get the migration done quickly and we felt we
were in good hands with RUBICAD's service division.
???
What
do you like about using RUBICAD's design service?
RUBICAD met all their commitments: We
asked for 30% area reduction, you said it would reach 30% reduction, and
you delivered as promised. We asked for 10 days turn around time, and you
did it in less than that. I think we could not ask for more. We are very
pleased.
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