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Alpha CPU goes 0.13 micron
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Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

Qualcomm creates optimized Standard Cell Libraries for any fab using Rubicad's LACE

How Qualcomm's ASIC group benefits from the latest and most advanced technology without the drawback of steady technology changes

Illam Pakkirisamy, Qualcomm Inc., San Diego, CA
Michael Reinhardt, RUBICAD Corp., San Jose, CA

Introduction
In the competitive, fast-changing semiconductor market, IC design centers and fabless IC design houses must be able to respond quickly to new, more advanced technologies. Today, standard cell libraries are the core on which most designs are based. Specially if there is a major technology migration the question is-What is the best choice? Use a library from a third party vendor or build your own library. Key issues must be evaluated and tradeoffs need to be made.

One thing is certain: The short time it takes to introduce new silicon fabrication technologies causes a change in the traditional way libraries are designed. The following discusses the options of using different library sources and shows how Qualcomm optimized their libraries using LACE, Rubicad's Layout Conversion Environment. As a result, Qualcomm was able to switch automatically to different fabs, process technologies and different voltage applications.

With Rubicad's LACE, Qualcomm saved costs in several different areas. First and most importantly, new libraries are available in a fraction of the time it used to take, and therefore new products are in the market several months earlier. Second, the converted libraries are not only available several months earlier, but the library elements are significantly smaller than they were with the old way of library conversion. This leads to die size reduction and wafer cost reduction. Third, the libraries were optimized for each  fab to achieve higher yields and a shorter signoff process.

Third party libraries - a comfortable way to create IC layouts
The big advantage of buying a third party library is that a company may not need to have in-house design capability to design and maintain libraries. Third party libraries are delivered with the different views and models needed for place and route, verification and simulation. The third party library provider takes care of the test chips and models.

These third party libraries usually are designed either for high speed or low power to fit into as many applications as possible. Library providers provide customization of libraries for specific customer needs, but that depends on how much money the customer is willing to pay on top of the library price.

Most third party vendors offer only foundry and technology specific libraries. This is very costly if a company needs to shift their design to a different fab for a second source, volume or price reasons. One option used to make the library fit with different fabs is to allow more area to accommodate a broader layout rule set. Reducing this area, in many cases, means using a custom layout. Custom layouts mean more manual work that results in a time consuming effort and are often the reason for large delays in library design.

Third party library providers are faced with the challenge that the technology introduction cycles are shorter than the time needed for a new library development. At the same time the product life cycles and market windows are decreasing. Therefore, the time to design libraries and bring them to the market is very critical.

In-house libraries for those, who want to be in control
If a company has high volume products, the option of creating their own standard cell library might be the most economical choice. The precondition is that the company must have a design team in place with experience in defining and designing libraries.

Another advantage of creating a proprietary library is that the library can be optimized for the specific needs of the applications. The library can be optimized for the power, area and speed requirements. Special customized cells are created for the design optimization.
In addition, the cells designed in-house can be suited for the methodology that is in place to have a smooth ASIC design flow, where multiple tools from different vendors are used for point tool solutions to achieve optimal designs.

Highly competitive markets are forcing system houses to cut costs per die by reducing die size and yield.  To get the smallest possible cells within the given parameters its best to choose the custom approach over the generating approach to create the libraries. This means manually drawing the standard cells to get the densest structure to achieve the smallest area.

Creating a customized standard cell libraries in-house might be risky, so many companies chose third party libraries.

Fabless design houses need to decide in advance which they will use. In today's highly competitive IC market selecting a cheaper fab might be a question of staying in business or not.

Therefore many companies who create their own library have chosen the so-called fabless library model. They create a subset of the design rules and design parameters from different fabs. The challenge is to create the library in such a way that it passes the final design rule check at the foundry where it will be produced. If that is not guaranteed in the beginning, there might be a delay just before the chip goes into production and much finger pointing as to whose fault is it-- the design team's or the fab's.

The major bottleneck for a customized library is the time consuming effort needed to create the physical layout of the library. The creation of a customized library is manual work. Official numbers range from one to 10 days per cell depending on the complexity of the cell. Even if a company hires several layout designers for drawing a new standard cell library it takes months to create the new library.

Considering today's fast changing process technologies layout designers are faced with the risk that, after the layout work is done, design rules might change because the process was not finalized when they started the layout design. If minimum design rules become smaller in a later design stage the design will still function. But if for example the metal pitch becomes 20% smaller in a later stage of the process development, the library could be 10-20% smaller. 10-20% area difference is a huge percentage in times of decreasing profit margins.
On the other side, if after the process final design rules become bigger, the layout designers have almost double the work to adjust the layout, which ends up in delays.

Nevertheless, a company who creates their own library has more control over area and performance metrics, the Spice model validation, the power numbers, the quality standards and the critical physical adjustments to enhance yields.

In the past the switch to a more advanced technology or to a different fab was done by a linear shrink method and manually fixing the remaining design rule violations and manual adjustments for timing. This linear shrink method doesn't work for most processes below 0.35 –micron, and therefore a different migration approach is needed.

This is a real dilemma for companies who create their own libraries as well for third party library providers when they shift to next process. A less aggressive shrink on the library is done very fast but will sacrifice area. A more aggressive shrink means more manual effort is needed to fix the design rules to achieve a more optimum area, but it requires more time.

Standard Cell Library Requirement for System-on-a-Chip Designs
Shorter and shorter process lifetime, a highly competitive foundry business and decreasing product life cycles require an economical approach to library migration. The traditional library model is no longer sufficient. There is a need for more library options even on the same chip.

During the tapeout phase, when a design rule check exists in the physical library, it is a difficult problem to solve, for the people who use third party libraries as well as for design teams who created their own libraries. A fix can take several months. This results in time-to-market delay.
This delay could be the death  for the product or even worse for the company.
Design companies and manufacturers must eliminate these risk factors and choose an approach to combine the area/speed/optimization benefits of full custom libraries with the benefit of fast turn around time of  a synthesized layout.

Why Qualcomm creates their own standard cell library
After evaluating the option to build or buy our standard cell libraries we at Qualcomm had the desire to be in control of schedule, performance and die size. We had to decide the right mix of performance, area reduction and power of our standard cell libraries. The right mix is key in providing a superior product that exceeds performance requirements, permits a smaller total die area per chip and works for low power applications. In each of these areas, there is a list of metrics we must balance. In other words, we have to make intelligent tradeoffs.

At Qualcomm we create our own libraries because we need to control and optimize for our design flow and applications. The libraries need to match our tools. We also setup our own guidelines for the cell design. There was an initial investment in developing the library, but with our high volumes, the overall costs are lower than buying an external library.

Creating our own library with unified design rule set causes trouble
When designing a library we define up front the  library's power and performance metrics. Our design teams do not know in the beginning which fab they will use. Therefore,  initially we use a fabless model and create a library with a common rule set for different foundries.
To meet the final design rule check of the different fabs, we rework the digital design and layouts, otherwise there is the risk of a critical time delay for the final production.

Best Results with own fab specific libraries
Designing a library for several fabs is a compromise. You need to figure out what is the optimum rule set that meets the requirements of each fab's signoff process. You need to figure out what is the optimum power for the fab and your design to meet your circuit specification within every fab.
The final design signoff might be time consuming because of many iterations and because the fabs and our teams checking tools are not completely compatible.

The best solution is to create a library in the fab specific rules. Time consuming spreadsheet calculation would disappear and the library could be optimized in area, performance and power.

Doing that in the traditional way by manually fixing all physical parameters in the layout is out of question. We need to go to different fabs simultaneously. Therefore we looked for a method which provides us with manual re-layout quality in a very short time.

Having the right methodology and tool suite in place minimizes the risk
We found the solution in Rubicad's LACE, a layout conversion environment. LACE satisfies our requirements for area reduction, time saving and most important cost savings.
LACE optimized our physical layout for our standard cell libraries for any fab or process technology within two or three weeks and without compromises in quality.

Here is what we did:
We started with our existing standard cell library, which was manually drawn in a 0.7-micron process technology and optimized for our requirements. This library was converted with LACE within our four-week time frame to a new 0.26 micron and to a 0.35-micron process technology.
Within the two week time frame for each process,  LACE was setup for our layout style and guidelines. To assure correct technology file setup we run external design rule and LVS checks with our standard check tool. Once LACE was setup; the library was run overnight and the next day we had a complete library layout in the new technology. After the first run we found out that we need to change the minimum gate length, but with LACE that was not problem. One number needed to be changed and within hours the whole library was corrected.
During this conversion LACE matched all the topics of our multi page design guideline for standard cells and  fit smoothly with our design tool set and design flow.

In the past when we converted to a different process technology we did a linear shrink and manual design rule fixing. During the first conversion with LACE we ran our traditional shrink approach in parallel. The comparison between the two converted libraries, one manual and one converted with LACE, was convincing for several reasons:

First, LACE compacted our layout to the densest possible structure so that we could significantly reduce the number of feeds in almost every cell in the x-direction. Therefore, the cells converted by LACE were on average between 20 and 30% smaller than the shrink cells.
Of course our layout designer could have made our shrinked and manually corrected cells smaller, too. The drawback is, that the manuall work needs four to five time longer than the automatic conversion method.

Second, the automatic layout conversion of a library using LACE needed only 15 to 20% of the time used for manual fixing. And the shrink with manual fixing did not end up with the smaller area, without sacrificing on time.

After the conversion of the library using LACE, the layout was LVS and DRC clean. We checked each cell visually to convince ourselves of the quality of the layout. Then we ran the same extraction and characterization flows which we always do. We extracted resistance and capacitances and did characterization. Within a week we brought the new library back into the design environment and used it with our place and route tools.

Cost Reduction - the most compelling reason to go a new way
As a fabless design house Qualcomm's ASIC design center need to get the best fab deal possible. LACE allowed us to take advantage of a compelling offer within a short time frame, because we could switch quickly to another fab and at the same time optimize our libraries not only for area but also for performance and yield.

What's next?
LACE's fast conversion time opens up several new design possibilities for us. It can be used to create libraries targeted toward specific applications by defining design parameters, such as transistor width and power bus width, according to the needs of the particular design. For example, libraries can be created for small, medium and large circuits, high-speed or low-speed, and high- or low-voltage applications. Designers can also create personal libraries containing only the cells they need for a particular design, so that those cells can be re-compacted for optimum size.

LACE can be used to convert whole blocks of pre-routed standard cells, or full custom macro blocks. In performing the layout conversion, LACE maintains the same relative positions of the devices inside the layout and the same relative capacitance and resistance. It reduces power consumption in pre-routed standard cell blocks by adjusting transistor sizes as needed.

With LACE, layouts can be converted to a new fabrication technology without human knowledge or understanding of the layout's circuit details. That is very important for us, because we use third party circuits that were not designed by our team. We needed a method to automatically shift and optimize those IP blocks for latest process technologies.

In deep-submicron technologies the grid values are becoming smaller and smaller in comparison to the geometrical structures. It is very time consuming if layout designer have to draw with 10 or 20 nanometer grid. Here we are going to implement LACE as a tool to accelerate manual creation of layout, by not requiring layout designers to draw layouts with too much focus on the fine details of the design rules, but rather on the quality of the layout, and then using LACE to update the hand-drawn layout to produce design rule correct layout. This way LACE is a big win for our layout team.

LACE performs the conversion automatically by treating the layout like an intelligent linear shrink that considers the exact design rules and the electrical relationships between the source and target technologies.

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