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Alpha CPU goes 0.13 micron
Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
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Synopsys chooses RUBICAD's LADEE for Layout Migration of 0.13u Memory Compilers

An Interview with Mike Keating, VP of R&D Design Reuse at Synopsys by Gabriele Eckert

??? Two years ago together with Pierre Bricaud you published the famous Design Reuse Methodology Manual (RMM) for system-on-a-chip designs. The RMM covered the design methodology for designing reusable blocks and for integrating reusable blocks into large chip designs. The main focus was on developing reusable synthesizable blocks. At that time layout migration technology was not a part of the reuse methodology which you described in the manual. What made you look into layout migration technology for design reuse of hard macros?
Because my responsibility at Synopsys changed. Originally I was responsible for the DesignWare Engineering Group, which was exclusively chartered to look into synthesizable blocks. The team was originally put together by the synthesis group to develop adders and multipliers and other synthesizable blocks that need a special kind of generator. The appropriate methodology was to use VHDL and generators to generate these regular structures in a synthesizable format. A little less than a year ago I was given the responsibility for the silicon library group. This group develops standard cell libraries, memories and I/O libraries for a variety of customers. One of our key challenges there was to look at the rapid migration of memories, in particular from one technology to another. And it was clear to us that we need to acquire the key migration technology that allows us to migrate the memory without having a large group of layout people, which would have been a challenge to put together in a reasonable amount of time. We were looking for a cost effective solution of the problem.
??? RUBICAD is working with your team on a design reuse project of physical mask layout. Can you tell our readers about the project?
We were working with RUBICAD's team to port our current memory family to a customer's 0.13 micron technology as a part of a major contract we have with them. One of the key compelling events we had is the deadline of a test chip. We had a very short amount of time to migrate two memory families: the single-port and the dual-port of static RAM. We felt, that the only way to do that was with automated migration tools.

??? What was the challenge to migrate the memory to the latest 0.13 micron technology?
There were several challenges which did not allow a simple linear shrink to the new technology: First, some design rules changed by 9%, some by 15%, and the overall shrink factor from our existing design to the new technology was 33%.
One big hurdle was the grid. Our memory existed in a 5-nanometer grid and we had to go back to a 10-nanometer grid. Thirdly, we had an area rule which did not exist in the original layout for several layers and for hole structures. 
One major change was that the new technology did not allow 45-degree structures in any layer, but the existing layout had lot's of 45-degree transistors. Using LADEE, we could straighten them automatically. Another requirement in the new technology was, that we had to add vias which were not in the original layout. Last but not least, we had to adjust the original layout to follow the size of the new bit cell which was provided by our customer. The changes were quite significant and it would have taken a huge effort to do these changes manually.

??? How would you master the challenge without a sophisticated layout migration technology like RUBICAD's LADEE?
We would have to put a large number of mask designers on the project. We believe even with a large number of people we would not have been able to meet the deadline. There is no way we could have made both the technical and the deadline challenge without RUBICAD's automatic layout migration technology. Eventually, we could have made the technical challenge by putting more engineers on the project, but never the deadline challenge.

??? Why did Synopsys chose RUBICAD's technology and solution for layout migration?
There is a relative small number of companies which provide layout manipulation technology. We did a technical analysis of the tools that were available. One requirement for the migration of our memory was that we could do the migration in a hierarchical way.
We also looked to the people in the companies which provide migration technology and the degree of cooperation we would get. We know that our first critical project would require a significant amount of support from the vendor. We saw that RUBICAD provides the best combination of the technical solution and the support we would need to get the job done. We definitely made the right choice. 

??? What is the biggest benefit of choosing RUBICAD's technology for layout migration?
In terms of choosing a layout migration tool, the biggest benefit was to meet the schedule deadline. In terms of specifically choosing RUBICAD's technology, the benefit was that your hierarchical migration technology is reasonably mature and ready to apply to the job. Also, the support we got from your technical team to get the job done within the given schedule is a great plus for us.

??? What did your people like most about the LADEE tool suite? 
According to Prashant Lokeshwar, one of the engineers working with the LADEE tools, the main pluses of the RUBICAD technology are the speed, ease-of-use, and LVS correctness. The speed means the speed of compaction and general turnaround time in comparison to other migration methods. He is also impressed with the speed of the layout editor functionality in comparison to other mainstream layout tools we use right now. A big plus is the general ease-of-use of the LADEE tool suite and the stability of the tools. For hierarchical compaction of memories, the most time saving feature is the HierO (Hierarchy Optimizer) tool which allows a fast analysis of the design for bottleneck cells. Without HierO, the manual layout analysis for finding the bottleneck cell would take hours.

??? What was your experience working together with RUBICAD's team on the layout migration project?
We learned that working with state-of-the-art migration tools is a complex business and takes a significant learning curve. Our engineers received an excellent hands-on training on the LADEE tool suite. The support RUBICAD offers is absolutely fantastic.

??? Do you have plans to utilize RUBICAD's layout migration technology for other types of projects?
Yes, we will certainly examine the application of RUBICAD's technology to a variety of other projects. Currently, our biggest challenge is memory migration, and we are throwing our biggest and most complex problem at the RUBICAD tool. We also have some other areas we are looking at. We do core, standard cell and I/O migration now with a combination of other tools and manual efforts. We are looking at the possibility of using RUBICAD's technology for that. Perhaps more exciting is that we are looking to other more complex blocks like analog designs and physical layer interface designs that we may offer as a part of the library. For migrating those blocks RUBICAD's technology is a very interesting option.

??? Do you plan to include automatic layout migration technology for the reuse of hard macros in the next version of the Design Reuse Methodology manual? 
That would certainly be one of a small number of topics we will consider to adding into the next version of the RMM. It's clear that synthesizable blocks cover a large proportion of a chip in terms of chip area. But there is a mixed-signal component to every chip that is absolutely essential and often that involves a design that is not synthesizable. And we need to address that part in the RMM. Again, I am thinking about how to address the migration of serializers, deserializers, DAC, ADC physical layer interfaces, PLL and PDDs, all of these issues. A number of readers of the RMM asked about mixed-signal. With the large amount of integration we do today, virtually every chip has some analog or mixed signal component. As long as the RMM is not addressing this issue, it is not addressing the entire reuse problem. 

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