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Infrastructure for Design Reuse
Solve Timing and Signal Integrity Problems
An Effective Way of Design Reuse

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During the last 20 years, shifting an IC design to a more advanced CMOS technology always resulted in faster circuits. But today, shifting a design to ultra deep sub-micron (UDSM) technology with 0.18-micron gate lengths does not guarantee a faster design. This is because accurate timing simulation can only be done after the physical mask layout is available for the ultra deep-sub-micron technology. But what if the physical mask layout does not meet the specification and the chip cannot compete in the market? Fabless companies need a flexible layout correction approach so they can automatically adjust the mask layout to the target requirements for timing and for signal integrity problems such as crosstalk. This article gives an overview of the various causes of the timing and crosstalk problems and discusses how to solve them in a practical way.

Voltage drop cause and effect

The technology changes from 0.35 microns to 0.25 microns and from 0.35 microns to 0.18 microns face far more challenges than any of the technology shifts that occurred between 2.0 micron and 0.5 micron. The reason is that, besides the geometrical changes of design rules, there are also changes in the electrical parameters in sub-0.35-micron technologies. These changes are a significant drop in supply voltage levels from 5V in all previous design technologies to 3.3V at 0.35-micron, 2.5V at 0.25-micron, and 1.8V at 0.18-micron technologies. The reason for this voltage drop is the necessary reduction of the gate oxide thickness because a higher supply voltage in these technologies would simply destroy the transistor gates.
But the paradox results that a thicker gate oxide reduces the switching speed of the transistor, when increasing its switching speed is the main reason for evolving technology  in the first place.

Area reduction and the implicit tradeoffs

At the same time, the overall dimensions of the circuit should be reduced to implement more transistors on the same area, in order to implement high-frequency system-on-a-chip designs. A smaller area implies reducing the pitches of the metal wires and increasing the number of metal layers. Further reduction of metal pitches reduces the distance between wires and it reduces the width of the wires. The reduction of the width has to be compensated by increasing the relative material thickness. But a thicker material and a smaller distance between parallel wires will significantly increase the fringe capacitance between wires. Increased capacitance is now an additional problem that must be coped with.

The undesired timing problems

These changes in deep sub-micron technologies are the causes of what some people call the timing crisis or design crisis in deep- and ultra-deep-submicron. The effects in design are that delay times between gates are dominated more by the capacitance and resistance (RC) of the wires instead of the fan out or transistor gate capacitance of the transistors connected to the wires. There is no positive speed effect to be gained by simply shifting a design from a 0.25-micron technology to a 0.18-micron technology by doing a linear shrink. And there are more and more circuits that face serious crosstalk problems, especially in connection with the use of dynamic logic, pass gates and higher frequencies. The question is how these problems can be solved in an environment of shorter market cycles, shrinking margins and more complex circuits.

Solutions for better circuit timing

Technology-driven solutions

All semiconductor and equipment vendors are searching for new materials such as copper and low-k dieletric to reduce the drawbacks of UDSM technologies. These solutions are expensive to implement and always involve a technology shift. The use of copper and low-k dielectrics will only delay the problem to the next technology shift, but they will not solve it. What is needed is a better design process that is capable of letting designers explore the limits of each technology more productively.

Timing-driven design methodology for UDSM design

Before we go further into the details of the problem I would like to ask--and answer--two key questions.

1) What is the most important outcome of any design process? Of course, the answer is a mask layout from which silicon can be produced that meets the right specification. Ironically, most design methodologies concentrate on a high level of abstraction and do not even mention the mask layout.

2) How big is the timing problem? How large is the number of signals or nodes involved? In most designs, even when they are very high speed, only a small number of signals faces the problem of timing divergence and crosstalk. Nevertheless, it is hard to detect them and even harder to solve the problems they pose, especially from a high level of abstraction.

What is the difference between a mask layout with a problem and one without a problem?

Timing convergence and divergence

Timing convergence means that some sub-networks have an unbalanced delay or too high of a delay in relation to other parts of the circuits. It does not mean that all signals are too slow, only a few of them. In most cases these signals are long wires with high capacitance and resistance and a high number of gates connected to them.
The question now is how to make this signal faster. Basically, there are three possibilities:
First the size (W/L) of the driving gate for this signal can be increased, second  more buffers can be inserted, or third the RC of the wire can be reduced.
Let's discuss the three options in more detail:

1. Increasing the W/L will not help in many cases, because of the limitation of the wire resistance, and it will also increase the gate capacitance, which makes the driver slower.
2. Inserting additional buffers is a good solution when it can be done without changing the layout topology in total. When additional buffers are inserted on a higher level of abstraction it is likely that the new layout created from the modified netlist has solved one problem but created new problems with other signals. Additional buffers will also increase power consumption, which can not always tolerated.
3. Reducing the RC delay can be done by applying signal-specific design rules:
a) For example doubling the wire width will reduce the resistance value of the wire by about 50%, which will double the speed of the signal.
b) Increasing the distance between critical signals has a large effect on the fringe capacitance of wires. Doubling the distance will reduce the capacitance by more than 50%.

Crosstalk

In an IC design crosstalk, or the lack of signal integrity, means that one signal influences the voltage level of a neighboring signal.
Everyone can experience this effect with voice calls on telephone lines. In ultra-deep sub-micron, crosstalk becomes more likely because of higher frequencies, lower voltage levels, smaller distances between wires, and long parallel wires.
The two ways to reduce crosstalk are wire shielding with power and ground lines, or larger spacing between the wires. Wire shielding with power and ground wires works until a certain frequency. The reason is that shielding with power and ground wires will also increase the wire capacitance, and will slow down the signal, an effect that must be avoided in order to prevent timing problems.
Therefore, the better solution to avoiding crosstalk in deep sub-micron and ultra-deep sub-micron is to increase the spacing between critical signals.

Possibilities for implementing changes into the physical layout.

From the previous discussion it is clear that the most obvious solution for reducing timing constraints and signal integrity problems is a combination of applying signal-specific spacing and width, and inserting buffers or changing buffer sizes inside the physical layout. The available tools for physical layout modifications are layout editors, place and route tools and layout compaction tools.
In the past, the only solution for signal-specific layout changes was to use a layout editor and manually change the layout. This manual approach is very cost intensive, time consuming and error prone. 
Some place and route tools promote a timing-driven approach to take signal constraints into account. Here, the problem is how to generate the constraints in the beginning. Most place and route tools do not have any information about the layout inside the cells, because they use so-called abstracts, which will make it hard to locate the problems
related to signals inside the cells. In a full custom design, a place and route tool cannot help solve the problems.
The most promising are compaction tools which can modify signal-specific spacing and width as well as transistor sizing, while keeping the overall topology of the layout the same. The constraints calculation will be provided by extraction tools, timing and signal integrity analysis tools interfacing with the compaction tool. One integrated solution is RUBICAD's tool suite LADEE which combines layout design, layout compaction and critical signal extraction capabilities in a single tool suite.

Conclusion

To conclude, it appears that chip designers need to go back and learn about the basics of physics and electronics, because the capabilities of the high-level description, which describes mainly the logical part of a design, does not necessarily match the down-to-polygon-reality.
Remember, the most important outcome of the design process is an accurate layout from which silicon can be produced. The slogan "The layout is the design" just might be true.

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