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Xilinx migrates FPGA

FPGAs Shrink With Physial Design Reuse

Time-to-market requires fast and accurate design migration to new processes

John Mahoney, IC Design Manager, Xilinx, San Jose

In today's competitive and fast-changing semiconductor market, an IC design team must be able to respond quickly to new and more advanced technologies. Increasing design complexity, complicated by shortened time-to-market windows, have forced many companies to start physical design before technology parameters are stable.

With pressures looming, accurate design simulation and layout optimization has become critical as well as more complex.
To address these challenges, our team at Xilinx Inc. (San Jose, CA) devised a technology-independent IC-layout methodology with the help of an edge-based mask layout compactor that allows us to reap the area and speed benefits from submicron and deep submicron technologies.

The bad news 
Before we discovered LACE, an edge-based mask layout compactor from RubiCAD Corp. (San Jose, CA), we used linear shrink technology. To our dismay, we discovered that linear shrink is insufficient for deep submicron technologies. The relationships of device sizes, power-bus widths, clock widths, and other design rules for technologies smaller than 0.8 µm are different than those for technologies at 0.8 µm or larger. These differences limit linear shrink's ability to take advantage of the minimum die size afforded by technologies smaller than 0.8 µm.

The shrink factor for a linear shrink is determined by the worst-case design-rule differential between the old and new technologies. In submicron technologies, the design rules change in a non-linear way, so a linear shrink of the layout is a compromise in die size and density.

At the time, we feared our only alternative to reach submicron technology's full potential in area and speed for our full-custom and hand-crafted layout would be to layout every process technology and every application manually. We ran a test case that compared density and die sizes of hand-crafted designs in technologies with different design rules, for a gate-shrink approach. It quickly became apparent that performing this operation manually was not adequate. In addition, it would require excessive design time and drain our layout design capacity. Therefore, we looked for a methodology or tool that would automatically compact our existing hand-crafted layout to future technologies.

The good news--migration tools 
There are only a few products on the market that can compact an existing GDSII database independent of the design system and style. We tested many compaction tools for physical-mask layout and found one that met our needs for layout and design requirements: LACE.

The edge-based compactor takes each edge of an existing layout and places it in a new position according to the target technology's minimum design-rule dimensions and its device-sizing requirements. The edge-based compaction algorithm results in the highest compaction degree any layout compactor can perform and allows optimizing the layout for power consumption, latch-up, etc. It was exactly what we needed for the layout of FPGAs.

The two inputs to LACE are the physical-mask layout in GDSII and the design rules of the target technology. The output is also a physical-mask layout in GDSII. The logical functions and relative topology remain unchanged. The tool changes the layout dimensions according to the target technology's design rules and electrical requirements, such as transistor sizes and power wiring. The edge-based compaction algorithm gives detailed user control of the compaction and allows us to maintain the topology of the layout during a compaction flow.
The test case to test the LACE compaction method, we manually laid out one block in 0.5-µm and a second block in 0.35-µm technology to find out what we would lose in die area with a gate shrink. The result was that the 0.35-µm layout was 20 percent smaller in area than a gate shrink of the 0.5-µm layout. Then we had the LACE software automatically convert the 0.5-µm block to 0.35-µm, and the 0.35-µm block to 0.5-µm technology. Next, we compared the conversion results to those drawn manually by two of our layout designers.

We concluded that the LACE-converted layout was in the same range as the manually drawn layout in overall density and die size. The layout generated after conversion looked similar to the input layout, and the placement and structure of devices and wires were the same. LACE maintained all layout information during compaction.

In our test case, it was possible to calculate the maximum theoretical decrease from 0.5 µm to 0.35 µm and the minimum theoretical increase from 0.35 µm to 0.5 µm. Only three design-rule values changed during this conversion; therefore, only a gate shrink would be possible for this application. The theoretical size was calculated by counting the design-rule values that created the bottleneck in the layout. The results showed that the compacted layout area was within 5 percent of the theoretical optimum.

After running the first test compaction, we recognized that an edge-based compaction is not only useful for technology migration of IC layout--it is also useful for the initial design process. LACE can be used to perform the following functions:

Edge-based compactor in design process 
If the design cycle is longer than the process technology cycle time, we have to start without knowing the exact design rules of the fab that processes our chips. Because our layout is entirely drawn manually by our layout designers, it is very important that we have a methodology that allows us to automatically adjust the layout to the latest rule changes. LACE allows us to adjust the design to changing rules.

Edge-based compactor for automatic design-rule correction
Drawing IC layout in submicron technologies has become more painful because we now have grid values of 25 nm and below. Counting numerous small grid points slows the drawing process and leads to many DRC violations. Drawing the layout in conjunction with the compactor makes it possible to draw the layout with a larger grid and then compact to the correct grid and design rules. This saves time during the design process.

Layout optimization
Another advantage of the detailed control of the edge-based compaction algorithm makes it possible to optimize the layout without increasing the total area. Some examples are to add substrate and well taps, to add redundant contacts and vias, and to increase the power metal width.

Device and wire sizing according to simulation results 
During simulation of the circuit, we found that certain wires and transistors had to be sized larger than others because of electromigration and speed problems. With LACE, we could easily solve this problem by identifying the specific devices and wires and then sizing them with different values.

Implementing the new method in the existing design flow 
The first product we designed using LACE is in a 0.35-µm technology. The original design we wanted to compact was laid out in a 0.8-µm technology. When building a new FPGA in the latest technology with the LACE compactor, we had to be certain that all the individual layout blocks and cells would talk to each other after compaction. That meant the port positions for interconnect metal had to be fixed according to the port positions of the core cell, the configurable logic block (CLB). The port positions of the CLB were fixed by intermediate feed layers surrounding the ports. The feed layers were generated automatically and deleted after the compaction process.

Of course, the existing cells that were laid out in the 0.8-µm technology were not designed for a compaction approach. The cells had overlapping polygons at the border. For that reason, manual work was involved in preparing the layout blocks with clean borders.

After compaction, the various blocks were placed and fit together properly. One block, or cell, has to be the reference for port positions for other blocks or cells during compaction. We first compacted the "reference cell" and generated abstracts of the port positions to give a reference for the compaction of the other surrounding blocks. The abstract of the reference cell was placed together with the surrounding blocks. Then we compacted the surrounding layout blocks according to the port positions of the reference cell. Therefore, we could be certain the block ports fit together after the compaction. This abstract port-generation is a feature of LACE-STAR, the hierarchical version of LACE.

Using the LACE conversion approach, we applied the design rules of the specific fab to the layout instead of using the unified design rules. This resulted in an 8.7 percent smaller area compared with the unified design rules. Building the design in the traditional way would have resulted in an 8.7 percent bigger die size. A rough estimate for the pure layout design time is two person-months using the compaction method versus two person-years if the layout were to be re-drawn manually.

Success Criteria 
The following were important criteria for selecting a layout migration tool:

Non-linear modification
We wanted to reuse existing designs, but this was not possible because geometrical structures do not change linearly in submicron technologies. The transistor sizes may have to be adjusted. The edge-based compactor can modify layers independently of each other, and it can size transistors individually during the compaction. These possibilities allow us to reuse existing layout, even in process technologies below 0.35 µm, and to optimize the layout by increasing or decreasing special layers and devices.

Linear run time
Xilinx FPGAs are built from logical blocks that have between 3,000 and 8,500 transistors. LACE is the
only layout-compaction tool we found on the market that can compact big blocks of physical-mask layout with thousands of transistors in a reasonable time frame. The run-time of LACE is nearly linear to the number of edges. The performance is n * log(n) * k--where "n" is the number of edges in a layout and "k" is a factor smaller than 1, depending on the technology.

Maintaining performance 
Xilinx designs high-density, high-performance FPGAs. Delays in FPGA-based designs are layout-dependent. Density and performance have to be maintained during a layout-compaction process. Therefore, the placement of devices, the widths of the lines, and the width and length of the transistors have to be controlled during the conversion process. LACE meets these requirements.

Maintaining placement
The relative timing of our circuits before compaction is very close to the timing after conversion because relative placement is maintained. During compaction, LACE maintains the relative original placement of the devices and the relative lengths of the wires. With this result, the compacted layout is as dense (or denser, if not done in unified design rules) as the manually drawn layout.

Handling 45-degree structures
To achieve the highest density and smallest possible die size, the Xilinx layout is designed using bent transistors and wiring with 45-degree structures. LACE maintains these 45-degree layout structures. In submicron technologies, the 45-degree structures, which are sometimes bigger than the orthogonal structures, may require different design rules.

Maintaining all properties and ports
Xilinx FPGAs are built from regularly structured blocks. The compactor has to guarantee that the ports of the interconnect metal will fit together after compaction. LACE can maintain the port positions in x and y directions. Therefore, the blocks abut together after compaction without the need for a routing channel, and all porting properties in the input are maintained in the output.

This new approach fits smoothly into our existing design flow. It is almost the same flow used in the past, but LACE gives us more flexibility and has advantages for layout optimization and design. In the future, we can reuse the LACE technology files and the flow we set up during the first project in an automatic flow. To change technology, we will change only design rule values; then we can run any number of designs.

Benefits of using the edge-based compaction method Design time and required time-to-market are getting shorter, while absolute chip size increases during every technology shift. This gap has to be closed. With the LACE compaction method, physical-design reuse becomes a reality for us even in submicron technologies. As a fabless company, we can now compact our layout to the specific design rules of each production fab.

In submicron technologies, the time for verification and circuit simulation is now 30 to 70 percent of the overall design time.
If the physical design of a macro block is optimized for timing and power, this macro block should be able to be reused for the next technology without a long verification cycle. Reusing the physical design by compacting the design at the mask level will shorten this time by 50 to 80 percent. To benefit from 0.25-µm and smaller technologies in a reasonable time frame, a design reuse methodology that results in fastest turn around time is necessary.

As a result of this experience, we at Xilinx have established a clear layout policy that our designers have to follow. Our physical-mask layout will be designed in a way so that it is easy to compact to any other technology.

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