Articles
Infrastructure for Design Reuse
Solve Timing and Signal Integrity Problems
An Effective Way of Design Reuse

Success Stories
Alpha CPU goes 0.13 micron
Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
Philips migrates microprocessor core
Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

CrossSpeed solves timing, signal integrity and power problems in deep-submicron (DSM) technology by reducing wire resistance and wire capacitance on the physical layout level.

New Orleans, LA, June 21, 1999.....Rubicad Corporation, a leading EDA supplier of layout and migration tools for physical circuit designs, today announced the introduction of CrossSpeed, a new signal/power/timing constraint calculator for layout design in deep-submicron technologies.

The CrossSpeed constraint calculator provides a new methodology for adjusting the physical IC design to achieve the required performance in deep-submicron (DSM) and ultra deep-submicron (UDSM) technologies, and for avoiding or solving signal integrity problems. It is the only available commercial tool that calculates wire constraints for the physical layout to meet timing requirements at the physical IC layout level.

CrossSpeed can be applied to any design style, including full-custom layout and standard cell design, as well as datapath and memory design.
The tool is one of several that are seamlessly integrated into Rubicad's LADEE design environment. Another LADEE tool, the LACE Layout Compaction Engine, adjusts signal line width and distance according to CrossSpeed's calculations. CrossSpeed dramatically shortens the physical design process by eliminating the design iterations of place and route cycles or the re-design of manually drawn layouts which do not match performance specifications.

"In Rubicad's design service division, we do all kinds of layout migration projects," said division director Juzer Fatehi. "With the advent of 0.18-micron design rules, we saw that applying minimum design rules to a physical design is no longer enough. Recently, when we converted a multi-million-transistor microprocessor for a big semiconductor company to a 0.18-micron technology, we realized that the only solution to increasing the performance of the critical signals was to apply signal-specific design rules."

"Every designer who will design high-speed circuits for 0.18-micron and smaller technologies will run into timing and signal integrity problems, which can only detected on the layout level after a layout is completed," added Michael Reinhardt, Rubicad's president. "Our experience with advanced, ultra deep sub-micron technologies led us to develop CrossSpeed, which lets IC designers automatically adjust a newly-completed physical design to the timing and power requirements in a straightforward way by applying signal-specific rules."

Solves all three major DSM challenges
Timing convergence, signal integrity, and power distribution have become the uppermost problems in the minds of IC designers working with DSM and UDSM technologies, because the following major effects begin to occur:

1. Gate delays decrease, due to shorter gate length.
2. Interconnect resistance increases, because of shrinking wire width.
3. Interconnect capacitance dominates total gate loading.

These effects have a direct bearing on the performance of the design and require automatic adjusting of the physical layout to compensate for these effects.

Timing Convergence in DSM
Designers face big challenges while creating the physical design of an IC design to reach timing convergence in large DSM and UDSM designs. The reason is that, before the complexities of DSM, gate and transistor delays dominated interconnect delays. But in DSM, the dominating interconnect delay, together with a drop in supply voltage level from 5V to 1.8V, causes timing convergence problems.

CrossSpeed solves the timing problem by reducing wire resistance and wire capacitance on the physical layout level. CrossSpeed allows designers to assign signal-specific design rules for critical signals in the layout. The LACE Layout Compaction Engine applies these specific rules and automatically adjusts the layout to meet DSM timing constraints. This allows designers to automatically correct and optimize the timing of manually-drawn layouts, such as datapath, RAM and ROM designs. Place and route cycles can be minimized because the routing results can be adjusted on the physical level to meet timing requirements.

Signal Integrity in DSM
Signal integrity problems are becoming a big concern in DSM technology and already cost significant yield losses for companies in the high-performance MPU business. The increase of signal integrity problems such as crosstalk is caused by high coupling capacitance between wires and reduced voltage levels, combined with high-frequency signals.

CrossSpeed solves signal integrity problems by reducing the coupling capacitance between signals. It lets designers specify net-specific distance rules to ensure the prevention of crosstalk. The elimination of crosstalk between wires significantly increases the yield of high-performance circuits and reduces expensive post-silicon analyses, thereby reducing time-to-market.

Power Supply Problems in DSM
Higher circuit speeds, transistor counts and coupling capacitance, as well as lower supply voltage levels, are the causes of IR drop and metal migration problems. These problems can be solved by increasing the width of power lines to prevent metal migration, hot spots and voltage drops on power lines. Another solution is to reduce the coupling capacitance between wires which will reduce power consumption and cooling problems, as well as reducing supply problems. CrossSpeed introduces and calculates the constraints for enlarging the power busses and reducing coupling capacitance between wires to reduce overall power consumption. This leads to higher IC yields and reliability.

Availability
CrossSpeed runs on SUN, HP and Pentium workstations under SUN OS, Solaris, LINUX, and HPUX. Shipments begin now.

About Rubicad
Rubicad Corporation is the pioneer in developing automatic layout migration and design software. The company addresses the physical design tool market, and offers layout migration and design tools and services.
Customers include major international IC manufacturers, semiconductor and fabless companies and system manufacturers. For more information, contact Rubicad Corp., 1150 North First St., Suite 130, San Jose, CA 95112, 408-995-3334, Fax: 408-995-3335, www.rubicad.net, info@rubicad.com

###

LACE is registered trademark, LACEedit, LADEE are trademarks of Rubicad Corporation.
All other trademarks are the properties of their respective owners.

Back to Top