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At DAC 2001, June 18-21, Rubicad will introduce DECOR, a brand new physical design tool that shortens physical verification cycles for ultra-deep sub-micron technologies

Las Vegas, June 18, 2001.....Rubicad Corporation, a world-leading EDA supplier of layout, manipulation and optimization tools for physical circuit designs, today announces DECOR, a brand new physical design tool based on "hyper-cell" technology. DECOR will significantly reduce physical verification cycles in ultra-deep sub-micron technologies.

The name DECOR stands for Design Correction. Rubicad will host several one-hour seminars to provide technical details and success stories from customers which have already applied the new technology to hierarchical layout databases as large as 2 gigabytes. 

Dataquest on the Physical IC Design Segment 

According to Gardner Dataquest's "EDA 2000" report, the market for physical verification tools increased from $190 million (U.S.) in 1997 to $303 million in 2000, and is expected to grow to $488 million in 2002. DRC check tools alone, the largest part of this market, will increase to $180 million in 2002, a growth rate of almost 30% per year. Other significantly growing parts of this market are physical extraction and analysis tools for timing, power and signal integrity. 

Increase in the absolute number of errors in physical design

Concurrent with the growth of the verification tool market, computing power has also risen significantly: the same number of computers can process more layout data for verification. In spite of this, physical IC designs are becoming more hierarchical. However, since designs are also getting larger, the amount of physical design data which needs to be processed by verification tools will grow by 30 to 50% annually. That means that the number of errors that are detected by the physical verification tools will also grow by 30 to 50% annually, assuming that the average number of errors per megabyte of physical design data remains constant. In order to produce silicon, these errors must be fixed in a timely manner. 

Today's methods of fixing the errors on the mask level are manual layout editing, or repeated place & route cycles. Both methods are extremely time consuming, and it will be impossible to fix the physical design in a timely fashion by using them. 

Traditional ways of solving the major verification issues 

DRC: Correcting DRC errors usually requires manual layout modifications. These
modifications often lead to other DRC errors that are discovered in successive DRC runs.
Timing:  Timing errors can be corrected by inserting drivers, or by changing routing, 
device sizes, or wire width and wire spacing.
Power: Power problems can be fixed by reducing power consumption or by adjusting the power grid. 
Signal Integrity: Signal integrity problems can be solved by increasing wire spacing between wires or by shielding.

Most of these errors are detected by verification tools, and then fixed manually by layout designers. Considering that the number of errors to be corrected will grow by 30 to 50 % per year, a more automated solution than manual polygon pushing is required. 

New "Hyper-cell" technology automatically corrects the major verification issues

Even if a sufficient number of designers were available to do the work, there would still be the problem of maintaining the database’s hierarchy. The problem designers face is that one cell used in multiple instances may be corrected in one placement, but that correction itself will create new errors, both DRC and LVS, in another placement. Layout designers try to prevent this problem by copying the original cell under a different name, but this increases the database and makes it flatter. 

Rubicad’s new "hyper-cell" technology enables a type of "holographic" view of the cells, by which the environment of all cell placements can be observed in a single view. In this way, conflicts among different cell placements can easily be prevented, many iterations can be saved, and the original design hierarchy can be maintained.
DECOR can be applied to virtually any database size. It has already been applied to one customer’s 2-GB, hierarchical GDSII database. DECOR can automatically correct over 90% of all of the errors during the first run. In this specific case, the layout database was drawn with unified design rules that were shrunk to the final dimensions on the mask level.

Several design rules on different layers had to be corrected, in order to make the shrink feasible. Special problems were caused by some design rules which became absolutely larger than in the original drawn database. For example, the transistor endcap increased, and poly spacing became wider. Additional mask layers, such as local interconnect, had to be introduced which were not available in the input technology. 

Traditional physical verification tools could not fix these errors, they could only detect them.
Correcting all errors manually would have taken too long and the market window would have been missed. The only way to get the design to silicon in a timely fashion was to apply Rubicad's new "hyper-cell" technology.

Major Benefits of DECOR's "Hyper-Cell" Technology

• DECOR uses a unique "hyper-cell" approach which creates holographic views of individual cells and considers the context of all placements during checking and correction. 
• DECOR works on every type of hierarchical layout database. Even a partly flattened database can be handled hierarchically. The technology handles an unlimited number of hierarchical levels.
• DECOR can handle any size of database. Huge, multi-gigabyte, hierarchical databases can be processed in parallel on a network in the fastest possible time frame.
• DECOR modifies a physical design only where needed. All other polygons and design elements are left untouched.

Rubicad Corporation is the pioneer in developing automatic layout manipulation and design software. The company addresses the physical design tool market, and offers layout migration and design tools and services.
Rubicad 's design methodology, containing a layout modification approach, solves most physical layout problems. Many companies have adopted layout manipulation technology to reduce the effects of wafer shortages and create second-source wafer supplies. The same layout manipulation technology can be used to solve timing, power and signal integrity problems in order to reduce the number of design iterations. Layout manipulation technology is further needed to convert hard IP to different technologies and to enable a global design reuse strategy that will reduce time-to-market pressures. 
By providing best-in-class tools, effective design reuse methodologies, and TopQuality Service, Rubicad is the essential partner to companies that design for leading-edge technologies and systems-on-a-chip.
Customers include major international IC manufacturers, semiconductor and fabless companies, and system manufacturers.
For more information, contact Rubicad Corp., 111 North Market Street, Suite 940, San Jose, CA 95113, Tel. 408-995-3334, Fax: 408-995-3335, www.rubicad.net, info@rubicad.com

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