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HierO [he:ro:] shows the effect on overall area of a design for optimized and non-optimized hierarchical cells

San Jose, CA, October 25, 1999.....Rubicad Corporation, a leading EDA supplier of layout and migration tools for physical circuit designs, today announced the introduction of HierO [he:ro:], a new IP and layout evaluation and optimization tool for hierarchical IC layout design and design migration.

HierO analyzes and evaluates a hierarchical layout and calculates how much each cell contributes to total area. HierO shows how much impact the reduction of a specific cell has on the overall design size. HierO tells the designer exactly which are the restricting cells and their locations and the reason for the restriction. HierO automatically analyzes large hierarchical IC layout databases for area optimization. This was impossible before for a layout design engineer. It is the only tool in the market that traces the area restricting cells in a hierarchical IC layout and provides information for optimization.

HierO can be applied to any structured custom design, like datapath and memory designs, which should be optimized or migrated in an hierarchical way within the same or for different technologies. The tool is one of several that are seamlessly integrated into Rubicad's LADEE design environment. Using another LADEE tool, the LACE Layout Compaction Engine, designers can automatically modify the layout where-in HierO has identified critical cells in terms of area. HierO provides information about how near the migrated design is to the optimum area after a hierarchical migration and in which cells to look for further optimization.

"In Rubicad's design service division, we do all kinds of layout migration projects," said Division Director Juzer Fatehi. "During the hierarchical migration of memory designs, memory compilers or datapath designs, our LADEE tool suite compacts all hierarchical cells in parallel and synchronizes the interconnects and ports. HierO identifies in an automatic way the bottleneck cells which restrict the area reduction of other cells and gives the user direct information about which cell has an impact on the total area reduction and where to check for further optimization."

"It is much more economical that a designer spends time to optimize a specific restricting cell by 10% if this results in an overall area reduction of 8% than spending time to reduce another cell by 50% which is placed somewhere in the periphery and has only an impact of 0.1% overall reduction," added Michael Reinhardt, Rubicad's president. "Our experience with hierarchical design migration led us to develop HierO, which lets IC designers optimize a layout during hierarchical migration without knowing the layout design from inside-out. HierO shortens the optimization time of hierarchical migration by a factor of 10."

Hierarchical layout migration requires parallel compaction of all cells
The LADEE tool suite is the only design migration tool suite that provides the capabilities to migrate physical IC designs in a hierarchical way from one fab to another or from one process technology to another. During hierarchical migration using the LADEE tool suite, all leaf cells of a design are compacted in parallel to assure that the cells interconnections and ports are maintained. During the compaction all ports of different cells which are abutted in one way or another are synchronized. After the parallel compaction of the leaf cells the layout is automatically reconstructed.

This parallel and synchronized compaction approach results in smallest possible layout within the given layout structure. However the technology change may cause some cells to restrict others in the degree of compaction. In a memory design or datapath design which consists of hundreds of individual leaf cells, the dependency of the cells is not obvious for a designer. To identify the restricting cells HierO gives transparent information about the dependency of all cells and where to look for restrictions.

Identifying Area Restricting Cells in the new technology
During the hierarchical compaction of a structured custom design like memory or datapath, some cells might restrict the compaction of other cells because within the given layout structure and the new design rule requirements, a bottleneck cell may occur.
HierO identifies the bottleneck cell and compares the hierarchical compaction result with a the theoretical optimum for that specific design and identifies the cells that have the largest impact on the overall area.

Availability
HierO runs on SUN, HP and Pentium workstations under SUN OS, Solaris, LINUX, and HPUX. Shipments begin in November.

About Rubicad
Rubicad Corporation is the pioneer in developing automatic layout migration and design software. The company addresses the physical design tool market, and offers layout migration and design tools and services.
Customers include major international IC manufacturers, semiconductor and fabless companies and system manufacturers.

For more information, contact Rubicad Corp., 1150 North First St., Suite 130, San Jose, CA 95112,
Tel. 408-995-3334, Fax: 408-995-3335, www.rubicad.net, info@rubicad.com

LACE, LACEedit, LADEE, and HierO [he:ro:] are trademarks or registered trademarks of Rubicad Corporation. All other trademarks are the respective property of their owners.

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