Design Optimization
Speed Improvement
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Sucess Stories
Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
Philips migrates microprocessor core
Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

During the last 20 years, shifting an IC design to a more advanced CMOS technology always resulted in faster circuits. But today, shifting a design to an ultra deep sub-micron (UDSM) technology with 0.18-micron gate lengths does not guarantee a faster design. This is because accurate timing simulation can only be done after the physical mask layout is available for the UDSM technology. But what if the physical mask layout does not meet the specification and the chip cannot compete in the market? Since the layout is the foundation of wafer production, all the other steps in a complete design flow are worth nothing if the outcome is a physical mask layout that is not ready for successful wafer production. 
With the advent of UDSM technologies, creating a layout that meets the chip's timing specification becomes a challenge for IC designers.

What is Influencing the Signal Delay Time
The delay time is a function of the capacitance and resistance of the different elements of the design. These are: 

• Transistor resistance is defined by the W/L, which is the relationship between the transistor's width and its length. Transistor capacitance is defined mainly by the transistor's area: the greater the area the higher the capacitance. 
• Wire resistance is defined by the length and the width of the wire: the wider the wire, the lower its resistance. 
• Wire capacitance is a function of the area of the wire and the distance between it and other wires, as well as the overlap between the wire and wires on different levels. 

RUBICAD's TopQuality Migration Service - Your Competitive Advantage
RUBICAD's TopQuality Migration service uses the LADEE Tool Suite to optimize your design on the physical layout level. 

All other EDA tools work on a netlist level for modifying the W/L in order to reduce transistor resistance to make the signal faster. But increasing the transistor's W/L will also increase the capacitance of the input transistor, which in turn increases power consumption. 

Rubicad's LADEE Tool Suite, which includes the CrossSpeed module, is the only set of tools that can influence the resistance and capacitance of the wires and optimize critical wires directly in the layout.

Call (408) 995 3334 or send an email to service@rubicad.com and discuss your next design challenge with us.

Check out the success stories on this site and learn how other companies have leveraged their designs.

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