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Hard IP Migration
Cores and Macros
Memory and Compilers
Library Migration

Design Optimization
Speed Improvement
Yield Improvement
Power Optimization

Sucess Stories
Synopsys chooses RUBICAD's LADEE for layout migration of 0.13-micron memory compilers
Peregrine cuts design time and costs
IMI increases performance
OKI reuses Hard IP
Philips migrates microprocessor core
Qualcomm optimizes Standard Cell Libraries
Xilinx migrates FPGA

Yield Improvement By RUBICAD's TopQuality Migration Service

RUBICAD’s TopQuality Service offers a number of different ways for significant yield improvement. There are several kinds of failures that influence overall yield.

Design specification failure
Even though a design may be functionally correct and working, it might not pass the parameter tests, which check for power consumption, speed or other performance parameters. “Performance yield” can be significantly increased by increasing the overall performance level. For example, if power consumption is the reason for low yield, RUBICAD’s TopQuality Service utilizes the LADEE tool suite to reduce power consumption in the design process. This can be done by applying CrossSpeed to the layout of the circuit to reduce capacitance between wires and to optimize the transistors’ W/L. The reduction of wire capacitance and gate capacitance will also have a positive effect on average circuit speed, which will further increase the yield.

Optimum design rules
For ultra deep sub-micron technologies, it is very important to use the optimum design rules during physical design implementation. Compromised design rules used in combination with a linear shrink violate the optimum rules and cause significant yield losses. Test data has shown that a 5% violation in some rules can cause a yield loss of 10% or more. RUBICAD’s TopQuality Service utilizes the LADEE tool suite to enforce the optimum design rules, thereby maximizing yield.

Slack design rules
Foundries and IC companies have begun to define slack design rules for their process technologies. Slack design rules are recommended rules that should be used when space is available. Some design rules are more critical than others. For example, in some technologies the contact-to-gate spacing is very critical, so the recommended rule is to use fewer contacts to connect the source drain area of the gates, and whenever possible to use a 10% larger spacing. This change can result in a significantly higher yield without increasing the die size. 
RUBICAD’s TopQuality Service utilizes the LADEE tool suite that allows the implementation of such slack rules automatically and efficiently,without increasing the silicon area.

The LADEE Tool Suite can be used to improve yield in all of these ways within a single integrated design flow. The yield improvement can be combined with verification tasks, such as DRC or design migration, so that no additional design steps or iterations are required. After all, yield improvement is the cheapest source of additional dies!

RUBICAD's design and layout migration specialists work with your team to deliver best-in-class solutions. You reduce your development risk while increasing your ability to deliver designs on time. 
Call (408) 995 3334 or send an email to service@rubicad.com and discuss your next design challenge with us.

Check out the success stories on this site and learn how other companies have leveraged their designs.

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