Cross-Speed
The solution for signal integrity,
power and timing convergence problems.
Shrinking process technologies and increasing
design sizes continually challenge design methodologies. Before the complexities
of deep sub-micron (DSM) and ultra deep sub-micron(UDSM), gate and transistor
delays dominated interconnect delays, and allowed the use of simplified
design methodologies that could focus merely on device analysis. But the
advent of DSM processes is changing all of this, and invalidating the assumptions
and approximations that existing design methodologies are based upon.
Today, signal integrity, power and timing
convergence have become the problems uppermost in the minds of designers
working with DSM and UDSM technologies.
This is because, as process technologies
shrink, the following major effects begin to occur:
1. Gate delays decrease, due to the shorter
gate lenght.
2. Interconnect resistance increases,
because of shrinking wire widths.
3. Interconnect capacitance dominates
total gate loading.
These effects have a direct bearing on
the performance of a design and require a change in design methodology
for automatically adjusting the physical layout to compensate these effects.
The CrossSpeed constraint calculator provides
this new methodology for adjusting the physical design to achieve the required
performance. The tool can be applied to any design style: standard cell
design as well as full custom, datapath and memory design. CrossSpeed is
tightly integrated into the LADEE tool suite.
The Cross Speed Solution
Timing convergence, signal integrity and
power problems have a common solution in the physical design representation:
applying signal-specific design rules to the layout.
Increasing the spacing of wires will reduce
coupling capacitance and reduce crosstalk. Reduction of capacitance will
reduce power consumption and increase signal speed.
Increasing the width of wires will reduce
wire resistance and therefore increase signal speed, or reduce voltage
drop and metal migration effects in power lines.
CrossSpeed intelligently calculates constraints
to reduce and eliminate the challenges in DSM designs.
Timing Convergence in DSM
Designers face big challenges while creating
the physical design of an IC to reach timing convergence in large
DSM and UDSM designs. The reason is, that before the complexities of DSM,
gate and transistor delays dominated interconnect delays.
But in DSM, the dominating interconnect
delay, together with a drop in supply voltage level from 5V to 1.8V, causes
timing convergence problems.
CrossSpeed solves the timing problem by
reducing wire resistance and wire capacitance on the physical layout level.
CrossSpeed allows designers to assign signal-specific design rules for
critical signals in the layout. The LACE Layout Compaction Engine applies
these specific rules and automatically adjusts the layout to meet timing
constraints in DSM. This allows designers to automatically correct and
optimize the timing of manually-drawn layout like datapath, RAM and ROM
designs.
Place and route cycles can be minimized
because the routing results can be adjusted on the physical level to meet
the timing requirements.
Signal Integrity in DSM
Signal integrity problem are becoming
a big concern in DSM technology and already cost significant yield losses
for companies in the high-performance MPU business. The increase of signal
integrity problems such as crosstalk is caused by high coupling capacitance
between wires and reduced voltage levels, combined with high-frequency
signals.
CrossSpeed solves signal integrity problems
by reducing the coupling capacitance between signals. It lets designers
specify net-specific distance rules to ensure the prevention of cross talk.
The elimination of crosstalk between wires significantly increases the
yield of high-performance circuits and reduces expensive post-silicon analyses,
thereby reducing time-to-market.
Power supply problems in DSM
Higher circuit speed, larger transistor
count and higher coupling capacitance, as well as lower supply voltage
levels, are the cause for IR drop and metal migration problems. These problems
can be solved by increasing the width of power lines to prevent metal migration,
hot spots and voltage drops on power lines. Another solution is to reduce
coupling capacitance between wires which will reduce power consumption
and cooling problems, as well as reducing supply problems.
CrossSpeed introduces and calculates the
constraints for enlarging the power busses and reducing coupling capacitance
between wires to reduce overall power consumption. This leads to higher
IC yields and reliability.
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