Hiero
The Area Optimizer for Physical IC
Layout
HierO analyzes and evaluates a hierarchical
layout and calculates how much each cell contributes to total area. HierO
shows how much impact the reduction of a specific cell has on the overall
design size. HierO tells the designer exactly which are the restricting
cells and their locations and the reason for the restriction. HierO automatically
analyzes large hierarchical IC layout databases for area optimization.
It is the only tool in the market that traces the area restricting cells
in a hierarchical IC layout and provides information for optimization.
Application to Any Design Style
HierO can be applied to any structured
custom design, like datapath and memory designs, which should be migrated
in an hierarchical way to different technologies.
Interoperability
The tool is one of several that are seamlessly
integrated into Rubicad's LADEE design environment. Using another LADEE
tool, the LACE Layout Compaction Engine, designers can automatically modify
the layout which HierO has identified as critical cells in terms of area
for a given design. HierO provides information about how near the migrated
design is to the optimum area after a hierarchical migration and in which
cells to look for further optimization.
Hierarchical layout migration requires
parallel compaction of all cells
The LADEE tool suite is the only design
migration tool suite that provides the capabilities to migrate physical
IC design in a hierarchical way from one fab to another or from one process
technology to another. During hierarchical migration using the LADEE tool
suite, all leaf cells of a design are compacted in parallel to assure that
the cells interconnections and ports are maintained. During the compaction
all ports of different cells which are abutted in one way or the other
are synchronized. After the parallel compaction of the leaf cells the layout
is automatically reconstructed.
This parallel and synchronized compaction
approach results in smallest possible layout within the given layout structure.
However the technology change may cause some cells to restrict others in
the degree of compaction.
In a memory design or datapath design
which consists of hundreds of individual leaf cells, the dependency of
the cells is not obvious for a designer. To identify the restricting cells
HierO gives transparent information about the dependency of all cells and
where to look for restrictions.
Identifying Area Restricting Cells in
the new technology
HierO identifies the bottleneck cell and
compares the hierarchical compaction result with a flat compaction and
calculates the impact of further reduction of the cell on the overall area
of the design.
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