| Silicon
Intellectual Property
Silicon intellectual property (SIP) is
one of the pillars upon which any design reuse strategy must be based.
SIP can be provided in two different forms: soft or hard. Each of them
has different characteristics, advantages, and areas of application.
Soft SIP
Soft SIP is represented by a circuit description
in a hardware description language (HDL) or a netlist. The most common
HDLs are Verilog and VHDL. These description are pre-verified on the functional
level. They may be accompanied with a test strategy and test vectors. What
is missing is the actual physical implementation. Soft SIP has many advantages:
Design changes
Designers can easily change the circuit
description of a soft SIP, provided that they have the knowhow and the
understanding of that circuit. Sample modifications are changing the size
of a memory block, the number of bits of a datapath, or the width of data
busses.
Freedom of implementation
A big advantage is the freedom of implementation
and choice of tools. The same VHDL model can be implemented using an FPGA,
synthesis and place & route, or a full custom approach. Because VHDL
is part of most design flows, soft SIP can be easily re-used.
Widely available
Because every design is based on a circuit
description (VHDL, Verilog, schematic or SPICE netlist), soft SIP is widely
available in any IC design company. These circuit descriptions can be easily
isolated from existing designs and can be automatically translated into
a different design format.
Easy integration using synthesis
During the synthesis process, different
soft SIP modules can be combined and melded into a new block, reshaping
the physical implementation of the block. The new block must be verified
and matched to the specification.
Hard SIP
The presentation of hard SIP is the physical
implementation together with a model for simulation and integration. The
blocks are most often complex designs such as microcontrollers, CPUs, DSPs,
memory compilers, or bus interface circuits. The advantages of using hard
SIP blocks are many:
Verified in silicon
Hard SIP blocks are usually pre-produced
in silicon and characterized blocks. Thus, designers can use the exact
performance and timing data for the integration process, and need not rely
on simulation results.
Optimized for a specific process technology
For high-performance circuits, such as
DSP or CPU designs, it is important that the implementation is optimized
for a specific process technology to achieve the highest speed and/or the
lowest power consumption. The area of a full custom integrated circuit
is often significantly smaller than the area of a design created with synthesis
and place & route. This is especially important for high-volume system
products in the communications and computing sector.
No detailed knowledge required
Designers working with hard SIP don’t
needto know the internal details of the circuit, because they don’t have
to synthesize and simulate the circuit. Designers can use hard SIP blocks
in the same way a PC board designer uses ICs. This frees the designer from
a lot of details and increases the number of applications for hard SIP,
because there are many more people available to apply it without further
training.
Better protection of SIP
Hard SIP provides a better level of protection
against copyright infringement than does soft SIP. Soft SIP is synthesized
for each application and has a different netlist and physical implementation
in each application. Therefore, it is difficult to prove any infringement.
Hard SIP has a specific netlist and often a very characteristic and unique
physical implementation, which can be easy identified.
Lower integration cost and shorter design
cycle
The cost of hard SIP is usually higher,
but it provides the advantages of lower integration costs and shorter development
cycles. This is because all of the synthesis, place & route and verification
cycles have already been done during the development of the hard SIP block.
Supporters of hard SIP say that its biggest
advantages are its process-specific nature and optimized implementation.
Its opponents say that the process-specific nature and inflexibility of
hard SIP are its biggest disadvantages. RUBICAD’s mission is to convert
these disadvantages into advantages by providing flexible migration and
physical design methodology for the reuse of hard SIP.
RUBICAD’s technology can be applied to
existing hard SIP or to newly created physical implementations of soft
SIP. This technology will shorten the verification and timing closure cycles
and can be used to optimize power consumption, signal integrity and yield.
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