LACE
The Layout Compaction Engine for Ultra
Deep-Submicron
LACE is the hierarchical compaction engine
inside the LADEE tool suite. LACE compacts layouts of all kinds: standard
cells, standard cell blocks, datapath, RAM, ROM, DSP and CPU cores. During
the compaction LACE intelligently considers the process design rules of
the target technology, as well as the user-defined and user-controlled
device sizing and wire sizing specifications.
During the compaction process, the layout
can be optimized to IC performance and yield. Such optimizations include
improvement of latch-up protection, reducing wire capacitances using signal-related
wiring constraints, contact optimization, transistor and power optimization.
Constraints for capacitance, transistor, and power optimization can be
calculated using other tools in the LADEE tool suite or importing external
tools via files or the Application Programming Interface (API).
Unique Features
LACE core technology is a fast, edge based
compaction algorithm that compacts an IC mask layout while maintaining
the same relative positions of the devices in the layout and the logic
function. The advantage of LACE's algorithm is that, unlike otehr compaction
tools, the runtime grows linearly with the size of the layout, instead
of exponentially. Tehrefore, users can convert large layout blocks in far
less time than it takes with tools based on other algorithms. Since LACE
can also distribute designs over the network, layouts of any size can be
compacted within a reasonable time-frame.
LACE provides easy-to-use wizards for setting
up technology and compaction parameters. This reduces the set up time for
a new technology from a couple of weeks to just a few days. The LACE tool
is integrated into the LADEE GUI, which provides a seamless integration
with the other tools of the LADEE tool suite.
Graphical User Interface
LACE's sophisticated yet practical GUI
allows users to interactively setup, execute and modify an automatic layout
compaction, conversion and layout optimization flow.
The LACE wizard asks the user question
regarding the layout style and uses those answers to automatically set
up the parameters for each specific layout modification task.
Hierarchical Compaction
During the compaction process, LACE maintains
an unlimited number of hierarchical levels even if cell borders overlay
or if routing goes over the cells on a higher level. LACE can hierarchically
convert structured layouts, such as memory, datapath design, and standard
cell layout, because of its sophisticated parallel scan line algorith.
Paralell Processing on the LAN
LACE’s intelligent Inter-ProcessControl
Algorithm allows the distribution of designs over the LAN, as well as the
ability to run a multi-level hierarchy compaction in parallel. Thus, different
portions of one huge design can be converted in parallel at the same time.
Device sizing
LACE performs non-linear device sizing
that is independent of the overall shrink factor. It allows sizing transistors,
wiring and other devices according to user-defined functions and equations.
This enables LACE to optimize a layout for the performance requirements
of the just-laid-out technology or another process technology.
Modifying contact number
While migrating a design to a different
technology, LACE can automatically increase or decrease the number of contactsas
needed by to the requirements of the new technology. The contact modifying
function can be user-driven or automatic.
Grid Independence.
LACE automatically adjust the grid of
a layout to any other grid value and allows to mix and match layouts from
different sources on a new silicon-system, even if the parts were laid
out with mutually incompatible grid values.
Analog Devices
LACE can extract and size analog devices
such as capacitors and resitors, as well as digital transistors. There
are no limitiations to the number of different types of devices, or to
the number of mask layers and design rules to define electrical devices.
Application Programmable Interface
The Application Programmable Interface
allows users to input customer-specific layout data in addition to the
standard GDSII format.
Ultra Deep Sub-Micron Design Rules
LACE handles all of the advanced design
rules which are showing up in deep sub-micron (DSM) and ultra deep sub-micron
(UDSM) technologies, such as minimum area rules, conditional rules, and
special rules depending on metal width.
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