LADEE
The Layout Design Environment for Deep-Submicron
LADEE is an integrated tool suite to create,
optimize, modify and verify integrated circuit (IC) design. LADEE combines
the generation and verification of physical mask design with timing and
power optimization on the physical level. This will shorten the design
cycle in UDSM technologies by achieving timing convergence, reduction of
power consumption and elimination of cross talk problems.
LADEE works directly on the physical database
without frequent iterations currently needed in traditional design flows.
LADEE solves the problem by removing or changing the cause of the problem
in the physical implementation of the design.
LADEE provides timing driven layout re-targeting
to new and different technologies by using the most advanced conversion
and verification technology available.
Infrastructure for Solving Timing
and Signal Integrity Problems in Deep-Submicron Technology
The common LADEE database allows to mix and
match all RUBICAD tools for creation, extraction, compaction, correction,
conversion, and verification of IC mask layout.
LADEE offers tools and modules for layout
analysis to meet the requirements for speed and power consumption for next
process technology. LADEE gives active user control over the interconnect
capacitance's created during the physical design process. Deep-Submicron
technologies of 0.25 micron gate lenght and below have shown that tight
wire capacitance control is needed to increase the performance. LADEE's
tool suite offers timing-driven layout design and reduces net-specific
cross-coupling capacitance to avoid or solve signal-integrity problems
like cross talk, optimizes power consumption and improves performance with
specific transistor and power sizing and wire spacing capabilities.
Layout Optimization and Migration
for Different Purpose
The LADEE tool suite automatically optimizes
the physical mask layout of complete chips or IC cores and macros for integration
and reuse in System-on-a-chip design in a new or different technology.
The LADEE tool suite automatically migrates and optimizes the layout of
standard cell libraries to fit for different process technologies and for
different voltage applications.
The LADEE tool suite adjusts a layout’s
structure to the electrical requirements to meet timing specification and
solves signal integrity problems like cross talk.
Following tools are operating under the
same database and graphical user interface:
Wizard is a task
oriented high level interface guide.
LACE is the layout
compaction engine.
LACEedit is
the IC layout polygon editor.
AutoMask is
a comfortable mask manipulation tool.
LayAna automatically
analyses an IC layout's hierarchy.
LayNet extracts
the hierarchical netlist of an IC layout.
BatchComp
allows to interactively setup a conversion flow.
CrossSpeed
calculates signal/power/timing constraints
HierO evaluates
layout for area optimization
P-REX inserts parameterized
cells into layout database
LADEE Applications
Layout Migration
LADEE provides extensive capabilities
for IC layout migration across foundries and applications. Layout migration
covers the conversion from one technology feature size to another as well
as from one foundry to another. The LADEE migration approach can be applied
to all kind of design style. Standard Cell libraries, full custom design,
memory, datapath design and standard cell blocks. During the migration
the layout can be optimized for performance by controlling transistor sizing,
wire resistance and wire capacitance. The migration process applies the
process specific design rules for optimum area results.
Optimization of Standard Cell Libraries
LADEE sets a new perspective to the library
business because it shortens dramatically the layout design process while
shifting to deep-submicron technology. Within days you can automatically
migrate and optimize the complete layout of a standard cell library for
a new process technology or a different application. LADEE provides tools
to analyze different migration options to optimize the area and performance
tradeoff. LADEE gives foundry customers fastest access to latest technologies
by shortening the library migration process from months to days.
Building System-on-a-chip and Embedded
Designs
LADEE provides the industry leading solution
for hierarchical conversion and optimization of layout cores and macros,
RAM, ROM, and datapath structures. The converted blocks can be easily mixed
and matched for system-on-a-chip or embedded designs.
LADEE shortens the design process of systems-on-a-chip
by offering the designer a reuse strategy for predictable hard macro. LADEE
overcomes the challenge of hard macro integration because it allows
to combine layout migration with performance adjustments in one integrated
design process.
Layout Design in Deep Submicron Technology
Sophisticated design rules and extremely
small grid values in deep-submicron have slowed down the layout design
process. Therefore layout design needs to be accelerated to hit market
windows and follow the fast change in process technology. LADEE provides
the environment to create full custom layout for deep-submicron even if
the latest design rules are not finalized. Layout designers can speed up
their layout design time by combining layout drawing with compaction technology.
The compaction process adjusts to the drawing grid and compact and automatically
correct the layout to the right design rule values.
Timing Convergence and Timing optimization
Timing convergence is often hard to achieve
in deep-submicron design with traditional synthesis centered design flows.
Static timing analyzes tools and simulation tools only highlight timing
problems in a layout without solving them. The LADEE tool suite solves
timing convergence problems by calculating physical constraints for wire
width, wire distance and transistor sizes and automatically adjust the
physical layout.
The direct correction of the physical
layout reduces or eliminates the needs of design iterations.
Power Optimization
Lower supply voltage levels, portable
applications and higher circuit speed demand for tight power wiring control
in the IC design to prevent IR dropping and metal migration problems.
Power optimization tools can calculate
new device sizes, hot spot locations and IR drop without fixing the problem
in the layout.
The LADEE tool suite automatically integrates
the results of power analyses tools, given by new transistor sizing and
power width sizing, into the layout.
Crosstalk Analyses and Prevention
Higher frequencies, lower voltage levels
and larger wire capacitance make crosstalk prevention a critical issue
for DSM designs. Designers have to detect potential cross talk situations
and transfer the findings into design changes without compromise speed
or chip area. LADEE provides algorithms for automatic detection and prevention
of crosstalk on the physical layout level. This solution works for all
design style from cell based automatic place-and-route to full custom design
styles.
LADEE – An Integrated Tools
Suite
Parallel Processing on the Lan
All tools of the LADEE tool suite can
operate in parallel over the lan. The Sequencer, an intelligent Inter-Process
Control Module coordinates the distribution of libraries and hierarchical
design over the network .
Batch Flow Composer
Inside LADEE all tools and function can
be combined in an automatic batch design flow. In this design flow all
tools work seamless together. The BatchComp provides a graphical interface
for selection of layout and design tasks which should be performed on the
layout. This capability helps design support groups to provide push-button
solutions for end users.
User Guidance
LADEE’s Wizard is a high level task oriented
interface that guides users through the extraction, compaction and optimization
process by using the LADEE environment for mask design and manipulation.
The Wizard automatically generates all technology and control files which
are needed to drive the design, compaction and verification flow.
The Wizard is user programmable and customizable
for specific layout and conversion tasks or specific user groups.
Interoperability with other tools
The Application Programmable Interface
allows users to input and output customer-specific layout data in addition
to the standard GDSII format.
LADEE is available for SUN OS 4.1, Solaris
2.5, HPUX 9.05 and Linux 2.0 (kernel) operating environment.
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