
| Technology
for
Design Migration Design Reuse Timing and Signal Integrity in UDSM Intellectual Property Physical Verification Library Generation Products
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LayNet
The Hierarchical Netlist Extractor for Ultra Deep Sub-Micron LayNet is the netlist extraction tool inside the LADEE Tool Suite. It extracts the transistor netlist from the layout data, so the netlist thus created is hierarchical. The netlist information is annotated to the layout, so that it can be accessed during the compaction process. The netlist makes it possible to consider net-related design rules such as spacing between the same or different nets, antenna rules, identifying power and clock inside the design, and defining signal-specific rules throughout the design. Because LayNet doesn't flatten the layout database during the extraction process, it can also be used for large hierarchical databases. LayNet can consider signal names inside the layout database and it can import signal names from a text file. These names can be used by other tools such as CrossSpeed to access the nets by name. LayNet reads and writes to the same technology database as all other LADEE modules. Besides the internal annotation of net information, LayNet can also create a hierarchical Spice netlist. |
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