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Standard cell libraries are widely used in most design flows. These libraries are usually hand-crafted physical layout cells combined with characterization and other data. The generation of a single library represents a major and costly effort in many semiconductor and fabless semiconductor companies. The design time for a single library of several hundred cells ranges between six months and one year, assuming a team of three to five engineers is available. The effort expended depends on whether the library is developed from scratch or is derived from an existing one using a linear shrink approach.

Another critical issue is the timely availability of the library in the design cycle. For circuits with design cycles of two to three years, a library designed for the final production technology is usually not available early enough in the design stage to do the logic design. 
To reduce the design effort and make the library available as early as possible, many companies buy libraries from third parties. These libraries are often incompatible with the existing one in terms of the number, functionality and characteristics of the cells.

For complex system-on-a-chip circuits, designers need multiple libraries for one design, because there are different circuit characteristics needed for different blocks inside the design. These libraries vary in the voltage level, drive strength, speed, power consumption, and size used to address the different needs of the blocks. These multiple libraries can no longer be created from scratch for each technology cycle and design, because of the effort and design time required. 
Therefore, automatic approaches must be used to generate these libraries. Such approaches have huge advantages, including: 

• The ability to start designs when technology information is not yet stable 
• The ability to create multiple libraries for different domains, such as low voltage, high voltage, high speed, low power, low leakage, high complexity, and low complexity 
• Libraries are compatible in functionality for easy migration of existing IP 
• Optimized grid for pins and routing grid 
• Optimized cell hight
• Optimized power routing 
• A reduction of design effort from person-years to person-weeks and months

This method is also ideal for working with uncertain or preliminary sets of design rules and technology information. When the fab is still not qualified or even built yet, but estimated target design rules are defined, this method can be used to design a preliminary library, which can later be easily adjusted to the latest rules.

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