RUBICAD | Technology & Products

Technology for
Design Migration
Design Reuse
Timing and Signal Integrity in UDSM
Intellectual Property
Physical Verification
Library Generation

Products
LADEE
DECOR
LACE
LACEedit
AutoMask
LayAna
LayNet
BatchComp
CrossSpeed
HierO
P-Rex

Design Migration of Physical IC Layout

Fast technology progress, the possibility of producing large systems-on-a-chip, and shorter market cycles for semiconductor products require new reuse-centered design methods and flexibility in chip production sources to stay within the economical boundaries of the business.
Since the limits of automatic synthesis for ultra deep sub-micron process technology have been discovered, there is a growing realization in the semiconductor industry that reusing predefined layout blocks, or so-called "hard IP," is the most cost-effective way.

The reasons for introducing a layout manipulation technology into a design environment to automatically migrate designs to smaller technologies or different fabs are:

performance
cost reduction with a smaller die or cheaper wafer source
second- or third-source production
design reuse in system-on-a-chip applications
shorter time to market
flexibility with late design rule changes

RUBICAD has performed extensive research and tests, showing that the highest-quality results in the shortest time come from a compaction method using an edge-based scan line algorithm. This algorithm is employed by best-in-class layout manipulation tools.
Today, layout migration technology must solve many problems besides providing a small, DRC-correct layout. Designers have to consider circuit performance, power consumption, compatibility with existing design flows, and design verification when choosing a layout conversion tool.

Compaction for Quality Results
During automatic layout compaction, conversion or optimization, layout quality is the highest priority. In most applications, quality means the wires must be as short as possible; there should be no long poly wires; source drain areas should be covered with as many contacts as needed; and double contact cuts should be made wherever possible.
The layout manipulation tool should be able to enlarge the power metal or fill up metal layers with dummy metal when needed. All structures must be on an exact grid, and some structures, such as ports or pickups, must be on a special grid to satisfy the needs of place and route tools. The best-in-class compaction tool suite LADEE can easily handle 45- degree and 90-degree structures. The user can decide whether to create, maintain or remove 45-degree structures. LADEE even handles 45-degree meander transistors very well. Automatic jog insertion can significantly increase the degree of compaction, but too many jogs will increase wire length. Therefore, controls for automatic jog insertion and removal are available. For controlling the quality of results, LADEE provides the following features:

Control of movement for each specific layer.
Definition of layer-specific grid.
Special grids for special structures.
Control for 45-degree and 90-degree compaction.
Optimized jog insertion and jog removal.
Clustering of structures.
Handling of orthogonal and 45-degree meander transistors.
Wire length and contact optimization.

Hierarchical Compaction
A layout is usually composed of small layout cells that form a hierarchical structure. Designers like to maintain a hierarchical layout database for reducing the amount of data and for flexibility in future modifications of the layout.
Hierarchical compaction using parallel compaction:
Solving the compaction for a multi-level, hierarchically-structured custom design, such as datapath or memory, is an inherent parallel problem, because each layout cell is placed with several neighbor cells. The compaction tool must now find the optimum layout that satisfies all placements of each cell. Parallel compaction can also handle over-the-cell routing and overlapping cells.

The LADEE Tool Suite handles complex hierarchical structures with the hierarchy extraction tool LayAna. LayAna automatically analyzes the hierarchy and rebuilds the layout in the new technology after the leaf cells are converted. Such an approach is also suitable for silicon compilers for RAM, ROM and datapath. The P-REX tool in the LADEE suite is used to maintain the most primitive cells (p-cells), such as contacts and gates.

Hierarchical Analysis and Optimization Capabilities
Designers dealing with hierarchical layout conversion have some special problems to solve. Some hierarchical designs contain several hundred base cells, and for most tools and designers it is impossible to do a detailed analysis of the quality of the overall design, because they must concentrate on every single cell. Therefore, analysis tools are needed to tell the designer how good the overall design is in area and where the design's congestion is located. RUBICAD's HierO gives designers detailed information about how much impact the optimization of specific cells will have on the overall design size. For a hierarchical design, this has to be done by analyzing the global database and highlighting details by the visualization of the constraint graph of the relevant base cells. Good implementations can reduce the analysis time by a factor of 10 or more.

The LADEE Tool Suite for layout migration, manipulation, conversion and compaction offers many features which allow designers to automatically modify a physical design and migrate designs to a new or different process technology.