| Physical
Verification
The physical verification of chip designs
has become more complex in recent years and will become even more complex
with the smaller process technologies that are now on the horizon.
One reason is the pure complexity of chip
designs, which has grown from several thousand to several million gates.
Another reason is the growing complexity of process technologies and the
demand for new types of checks that were not previously needed.
RUBICAD develops advanced solutions for
chip design verification which consider the latest demands of process technologies
and design complexity.
RUBICAD differentiates itself from other
vendors by developing solutions to automatically correct these errors in
the physical design.
DRC
RUBICAD’s LADEE Tool Suite can perform
an integrated DRC check. Aside from checking for DRC errors, the tool can
also be used to fix these errors where possible. This reduces the work
of correcting design rule errors to a minimum.
LVS
RUBICAD also provides an internal LVS
check to ensure that the converted layout is LVS correct. Future versions
will also provide a full hierarchical LVS.
Antenna rule check
Advanced deep sub-micron process technologies
require “antenna rule checks.” These are complex rules requiring the analysis
of the gate and signal capacity of the different layers for each signal.
The check itself is a complex task and the correction even more complex,
because it requires topological changes in the layout, such as inserting
diodes or local rerouting of wires.
With RUBICAD’s tools, designers can check
antenna rules and correct them by combining the analysis with the layout
modification capabilities of LADEE. This is particularly important for
physical design migration, when the requirements of the antenna rule change
from one technology to another.
RUBICAD’s approach works for full custom
design flows as well as for design flows using synthesis and automatic
place & route.
Metal density
Metal density rules define the density
of metal layers on the silicon. The rules have become more and more complex
with the latest process technologies and increased chip complexity. Automatic
correction using dummy material is required. With the LADEE Tool Suite,
the density correction can be automatically performed, whether the design
is a new one or the result of a layout migration check.
Signal integrity
High-performance designs in deep sub-micron
technologies are more likely to face signal integrity problems. RUBICAD’s
tools offer the capability to check for such problems and to correct them
by modifying the physical design.
RUBICAD’s technology offers the unique
capability of automatic layout design correction for DRC, timing, signal
integrity, power and other design problems. RUBICAD’s tools can be used
either alone or integrated into a single design flow together with other
customer-preferred analysis and simulation tools.
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