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Without a design reuse strategy, it will be difficult to compete in the semiconductor industry, especially at 0.18-micron and below. The choice of a design reuse methodology will be up to management, and the decision will be a significant one. Without reuse, system-on-a-chip (SoC) design is doomed to failure. This is because, in an SoC, many different functions and applications, each requiring specific know-how, must be combined onto a single piece of silicon. To do this in a timely manner, designers must reuse existing functions, blocks, and cores that have been pre-designed by experts, and integrate them into a new SoC architecture in the same way that board designers use pre-designed components. 
The bigger and more complex SoCs become, the more specialized they will be, which means lower volumes and the need for chips to be cheaper to design. Not to mention the need to get to market in time to meet demand. Without reusing pre-defined parts, SoCs will be too expensive to produce and impossible to bring to market in a timely manner. Somehow, today's intellectual property (IP) elements have to be created so that they can be reused in the same way that standard-cell library elements have been in the past. 

Soft or Hard IP?
A system chip is usually composed of a combination of hard and soft IP blocks. A design reuse methodology based on migration employs hard IP. If soft and hard IP are compared on a scale of value, it becomes clear that hard IP is superior because all of the verification and simulation work is already built into it, and silicon can be produced from it. The engineering time and talent required for reusing hard IP and migrating it to a company’s target process technology will be significantly lower, since what will be reused is an existing working layout of silicon-proven IP. The time required to integrate the converted hard IP into an SoC is minimized because the IP can be used as a black box (a migrated IP block becomes a white box because during the conversion the signal and power lines, as well as device sizes, must be adjusted accordingly). 
Of course, designers still need to simulate and verify a migrated design in deep sub-micron technology. But the starting point of the migration process is a working and silicon-proven design. Therefore, the relative timing is given, and the migration to a new process is straightforward. The migrated result is predictable, because the layout is migrated in such a way that a circuit's timing and speed are maintained or enhanced, and signal integrity problems are solved. 

Reuse Any Layout
With a layout migration tool suite like RUBICAD's LADEE, designers can reuse any piece of a layout, and the converted design will have the same density as a manually-drawn layout. This mask layout may be a full-custom manually drawn layout, or a routed standard-cell design or a combination of both. It is usually created and optimized for a specific technology and a specific fab. A big advantage of hard IP is that the provider can optimize the design element for power, speed and area. 
Optimized hard IP is often manually drawn. 
For those who don't use migration tools, a drawback of hard IP is that the layout exists for a specific technology, and has a specific grid and specific power and timing behavior. To reuse the existing layout of a hard IP element for a new SoC, the geometrical structures of the existing layout--design rules, grid, device sizes, width of power and signal lines, distance of power and signal lines-- must be adjusted to the requirements of the new process technology. This is precisely where the LADEE Tool Suite eliminates the drawback of hard IP.

LADEE compacts hard IP to new design rules, adjusts the width of signal and power lines to the performance requirements of the target process technology, and adjusts the grid of all hard IP components that must be combined on an SoC. All device sizes are adjusted according to the new process parameters, and signal integrity problems such as crosstalk are solved by differentiating between high-load and high-speed nets. 

The LADEE Tool Suite for layout migration, conversion and compaction offers many features which allow designers to automatically modify a physical design and migrate it to different process technologies for reuse in new silicon systems.
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