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During the last 20 years, converting an IC design to a more advanced CMOS technology always resulted in faster circuits. But today, shifting a design to an ultra deep sub-micron (UDSM) technology with a 0.18-micron gate length does not guarantee a faster design. In UDSM technologies, a significant change has occurred in the relationship between the electrical parameters of wiring and transistors. 
This problem is generally called the timing problem, which is actually a mix of several problems occurring at the same time. These problems are:

• Limitations of the typical synthesis-based design flow accompanying huge design sizes. 
• Increased capacitance in the wiring caused by the aspect ratio of the wires.
• Reduced supply voltage levels and circuit speeds caused by smaller gate length. 
• Higher circuit speeds, lower voltage levels, and greater capacitance cause crosstalk and transmission line effects, which can, in turn, cause circuit failures. 

The Timing and Signal Integrity Problem 
A closer look at the problem can be gained by considering a general traditional design flow that covers a variety of design styles, including full custom, standard cell, and datapath or memory design. This flow begins with defining a circuit on a higher level of abstraction in VHDL or a schematic. The next step is simulation of the high-level description and logic synthesis of a netlist. From the netlist a layout is created. 
From the layout, capacitance and resistance will be extracted and then simulated for timing and power. In previous process technologies of 0.5 micron and above, this design flow worked well and required about two to four iterations to reach a working mask layout. But UDSM technologies can require 20 or more iterations, because the ratio between wire delay and signal delay changes from 20/80 to 75/25. Thus, the delay in the wires can be 75% and more of total signal delay time and the gate delay is only 25% or less. These greater wire delays are caused by larger absolute circuit sizes, which means longer wires and higher capacitance, faster and smaller gates, smaller distances between wires, and different aspect ratios of the wires. The greater wire capacitance cannot be anticipated during logic simulation, because wire length is terminated by the place and route tool. In addition, signal integrity problems such as crosstalk are caused by higher wire capacitance and lower supply voltage levels. 

These problems are not exclusive to a synthesis-based design flow. Similar effects can be seen in full custom† designs. There, correcting the problems is more painful because a great deal of manual work is involved. 

The Physical Cause of the Problem
The picture below shows typical wire cross-sections of an 0.5-micron process and an 0.25-micron process. The wires in the 0.25-micron process are taller and narrower with a smaller footprint than in the 0.5-micron process. As the wires become smaller, the footprint and the distance between the wires also becomes smaller. To compensate for this, the wires become taller to handle the same or greater current density. These taller wires with less spacing increase the cross-coupling capacitance between wires significantly if the wire materials, and the materials between the wires, is not changed. Therefore, new materials, such as copper and low-k dielectrics, are being introduced into the latest processes of 0.18 micron and below. However, this will only delay the problem for another process generation. 

Increase in relative wire length 
The relative wire length can be expressed by the factor (wire-length/feature size). Because of the increase in design size from about 100,000 to 20 million and more transistors, the relative wire length is increasing. 

Voltage level reduction 
The reduction of the voltage level is forced by the thinner gate oxides that achieve faster gates. At the same time, voltage level reduction causes longer delay times for changing the signal level of the signals. 

How to Solve the Timing and Signal Integrity Problem
Delay time is a function of the capacitance, resistance and voltage level of the elements in the design. The lower the capacitance and resistance and the higher the voltage level, the shorter the delay time. Voltage level is usually determined by the technology and cannot be changed.

What is influencing capacitance and resistance? 
a) Transistor resistance is defined by W/L, which is the relationship between gate width and length. Transistor capacitance is defined mainly by gate area: the larger the area, the higher the capacitance and the longer the switching time. 
b) Wire resistance is defined by the number of squares per wire or by the quotient of wire length and wire width. The wider the wire, the smaller the resistance. 
c) Wire capacitance is a function of the size of the area of the wire surface and the distance to other wire surfaces. 
Capacitance grows with size, area, and the reduction of distance between surfaces. 

From these observations, it is clear that there are four possibilities for reducing signal delay: 

1) Increase the W/L of the source transistor. 
2) Reduce gate area of the target gate. 
3) Increase spacing between wires to reduce C. 
4) Increase width of wires to reduce R.

Until now, nearly all solutions have increased the W/L of the driving transistor because they operate on the netlist and cannot manipulate the wiring. The reduction in gate area of target transistors is usually not possible, because it will increase the delay of the output of that transistor. Manipulating the width and spacing of wires can only be done by a layout manipulation tool. This solution has the following additional advantages: 

• Increasing the width of wires and the spacing between them will only increase the speed and will not reduce the speed of input or output signals, as is the case with W/L changes. 
• Reducing capacitance will reduce overall power consumption. 
• Increasing the spacing between wires can also solve signal integrity problems. 

Features for Timing-Driven Compaction

Selection of critical wires 
There are basically two ways to select critical signals in the layout. Critical nets are defined either by an external source or by the LADEE Tool Suite itself. The external source can be the user, a timing simulator, or any other extraction method such as net length or net capacitance. For all of these methods, the interface to the LACE compaction tool is a list of net names or net coordinates. To use this information, the LACE compaction tool has an internal extracted netlist view for tracing the signals inside the layout. In many cases, designers who want to use a conversion tool don't know much about the internals of the silicon intellectual property (SIP] they want to convert. 
They also don't want to spend time on extended extraction and timing simulation. Therefore, LADEE has its own selection functions for critical nets. With this information, and the technology parameters of the source and target technology, the timing quotient for each net before and after conversion can be calculated. This information can be used to create an automatic feedback loop. As the process is linear, only one to two iterations are required.

Target performance specification of signals
The target performance for each signal can be specified as either absolute or relative. For the process of layout conversion, the relative specification is sufficient. This can be done by defining new spacing and width rules for classes of critical signals. The LADEE Tool Suite is capable of doing this in a different way for each layer and class, in order to reduce to a minimum any area penalty for spacing increases. The absolute specification lists the capacitance, resistance or delay time with the signals. This is useful for analog design and design tweaks. LADEE then automatically calculates the rules needed for each signal to reach the specification. 
The LADEE Tool Suite for layout migration, conversion and compaction offers many features which allow designers to automatically modify a physical design to solve timing and signal integrity problems in UDSM technology.

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